With IP-Cores without handshake protocol, how can I verify (VHDL assert?) their latency?

Question

I'm using an IP-Core of Xilinx that was generated using the Vivado IDE's IP Catalog, specifically I'm using the Accumulator and the Multiplier IP Cores.

These cores have a latency configuration of 6 and 3 respectively and do not use a handshake protocol (ready-for-data, done, run signals). When I'm using the cores with a component instantiation, I need circuits to handle the latency delays.

How can I verify that the latency is actually 6 and 3 respectively? Imagine that the IP Core is updated and the latency is changed, or in my code, I have it backwards and assume latencies 3 and 6 respecively. I want to assert component'latency = 3, or something similar. What's the way this is done?

Answer 1

If you need a guarantee that the design will not change with a future tool version, then don't use an IP core for this sort of relatively simple functionality. You can quite easily instantiate one or more DSP slices with a fixed configuration that will not change between tool versions. The DSP slice user guide has everything you need to know. Depending on your use case, you might be able to infer an optimal implementation using a simple x <= a * b;

You might find that in your application, you can time domain multiplex the inputs and mode for one set of DSP slices in order to achieve the same functionality with fewer resources; for example, do you need to multiply and accumulate at the same time? The IP core can never be aware of this.

If your primary goal is to get a design working quickly, then the IP cores will give an effective result.

Answer 2

As explained in my comment, you can just write this:

y0 <= a * b;
y1 <= y0 when rising_edge(Clock);
y2 <= y1 when rising_edge(Clock);
y3 <= y2 when rising_edge(Clock);
y  <= y3 when rising_edge(Clock);

Xilinx tools we use pattern matching and retiming as an optimization:

• instantiate DSP slices for your multiplication
• if needed combine multiple DSP slices
• move register stages into the DSP by enabling internal pipeline registers.

Up to 5 (or was it 7?) pipeline stages can be moved into the DSP48E2. Some might need to be described as registers before the multiplication.

The same techniques apply to accumulate operations.