Why isn't a depletion region considered at the P-N junction of a MOSFET?

Question

I'm trying to understand the working of an n-channel depletion type MOSFET. I'm confused why no tutorial talks about the depletion region between the P and N type silicon i.e between the 'bulk' and the 'channel'.

Even if I were to consider that the depletion region is actually present but neglected in the explanation, here comes the next question, 'How can the MOSFET ever work in the 'Enhancement Mode'?'

Because I presently understand that this MOSFET will be in the Depletion mode when I forward bias the P-N junction (the depletion region gets destroyed and holes shift towards the gate to decrease the carrier density) But for enhancement mode, when I reverse bias the P-N junction, the depletion region should further increase (become wider) and once again the channel should become SMALLER thus REDUCING the drain current, whereas the drain current actually INCREASES in the Enhancement mode (Transfer characteristics diagram attached). What am I missing?

Answer 1

How do enhancement mode mosfets even work: You are missing the creation of the "Inversion" layer. When you apply positive gate bias to an enhancement mode mosfet, the existing P channel near the gate contact starts to recede and you have your gate contact - depletion region - p substrate. If you keep going, the concentration of holes near the contact is so little, that you form, in affect a N region near the contact - A N channel now forms between the source and drain contacts.

So at this point, is you examine a cross section of the Enhancement mode mosfet, from source to drain you will see: N+ - N - N+. If you now look "down" you will see Gate - N - depletion - P.

Answer 2

People get into trouble when they ignore the movement of charge that is forming the channel. That charge has to come from somewhere. Typically there is a BULK tie/contact to inject this charge; the BULK may also be part of the reverse protection diode.

I've seen place-and-route projects that had to return to square-one and greatly increase the onchip BULK ties, because the sea-of-logic transients demanded so much charge from the (sparse) BULK ties that the propagation delays were horrid, and the jitter was horrid.

That 4rth terminal of the FET needs respect.