difference between sensitivity list and wait vhdl

Question

I have sample 2bit multiplexer implemented with processes with one little different, first one has sensitivity list and second one implemented with wait.
I want to know what is difference between this two code and which one of them is more accurate?

 ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
PROCESS ( a, b, s )
BEGIN
if s = '0' then
w<=a after 1.4 ns;
else
w<=b after 1.5 ns;
end if ;
END PROCESS ;
END Behavior ;

and the second code:

  ARCHITECTURE Behavior OF mux2to1 IS
    BEGIN
    PROCESS
    BEGIN
    wait on  a, b, s;
     if s = '0' then
    w<=a after 1.4 ns;
    else
    w<=b after 1.5 ns;
    end if ;
    END PROCESS ;
    END Behavior ;

Answer 1

The two processes as you have written them are almost equivalent. If you move the wait statement to the end of the second process, then they are exactly equivalent. The difference is whether or not the body of the process gets executed before the first change on any of the listed signals.

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IEEE Std 1076-2008 11.3 para 4 (in part):

If a process sensitivity list appears following the reserved word process, then the process statement is assumed to contain an implicit wait statement as the last statement of the process statement part; this implicit wait statement is of the form wait on sensitivity_list ; where the sensitivity list is determined in one of two ways. If the process sensitivity list is specified as a sensitivity list, then the sensitivity list of the wait statement is that following the reserved word process. ...

Answer 2

edit:

It seems Dave Tweed is right and I was wrong. Just try this simple example.

entity test_e is
end entity;

architecture test_a of test_e is
    signal test_s : bit;
begin
    process (test_s)
    begin
        report "process triggered";
    end process;
end architecture;

And simulate 1 time step. Even though test_s has no event, the report will still be shown.