thoughts on reading only one changing GPIO with accurate time amoung huge number of digital Inputs

Question

I am trying to read a huge number of digital inputs (129 to 800 and maybe more) at the same time. the sampling rate should be around 500K samples per second but I only need to read one of these inputs if there is a signal change (interrupt?). I am stuck at this for a long time and would really appreciate the help.

• should I use 16 bit PISO shift-registers IC and a simple MCU but it seems that I will have to check every bit looking for a high signal?.

• should I use an IO expander IC with SPI such as interface such as MCP23S17 but usually these have 3 bit address which mean I only could get away with 16*8=128 inputs. Another IO expander with greater IOs is MAX7301 but I am not sure how to use multiple ones and if it would affect the performance.

• should I move to an FPGA for this sort of jobs given that I never touched one but I am ready confront my fears.

• will multiplexers work or will they have their limits

• could a hardware cascade of ICs solve this issue so I only recive the address of the changing bit with timestamp but how?

it is important to note that I need to keep the sampling time high in order to capture any change in one or at most 2 pins. please point me to the right direction as I am clueless and don't know what to do.

Answer 1

A microcontroller with lots of pins as an intelligent I/O expander could be more cost-effective than an FPGA.

An STM32H743BIT6 has for example 168 I/O pins, let's say 8 of them are needed for communication and debugging, leaving 160 inputs for the application. These pins are arranged in 11 ports of 16 bits each. The controller runs on 400 MHz, so there'd be about 72 clock cycles to read and evaluate each port. There is 64k code memory with 0 wait state even at full speed, it seems plausible with some careful assembly coding.

You can connect a couple of these controllers as SPI slaves to a master MCU.

^{simulate this circuit – Schematic created using CircuitLab}

Each slave would scan its inputs continuously, and signal on the INT output whenever there is a change, then the master can poll that slave for the pin number(s). As a crude means of avoiding race conditions, the slave could suspend processing the inputs until the master acknowledges it by reading the SPI buffer.

Answer 2

Forgive my ignorance, but if a regular IC won't do it. could you point me to how to do it using an FPGA. which kit has this many inputs? a general idea of how to do it would be greatly appreciated.

Unfortunately what you ask falls under "design services" which is not what we offer here. So I will only some give guidance.

You can get FPGAs with up to 1400 pins. The bigger ones (>800 pins) are not cheap. I had a quick look and you are talking $1200 plus. You hardly need any logic (2000 registers or so) so it may be cheaper to use several smaller FPGAs.

Use a clock (500KHz or higher) to register each input and make an edge detector. Every decent HDL designer knows how to do that. As soon as an edge is seen store a counter value.

With such a larger number of pins I would divide the task in pin-groups and add some pipelining logic to find the two lowest counter values and subtract to get the difference. This is also beneficial if you use multiple smaller FPGAs.

This is only an outline, the actual task may be more complex because we don't know the details and every experienced engineer knows that the devil is in the detail.