There are many examples of logic circuits that have the clock signal, such as the JK flip flop and the clocked SR NOR Latch, but I still wonder what is the purpose of the clock. Why do people think of adding the clock signal into the circuit? Isn’t it simpler and easier to learn without the clock?
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\$\begingroup\$ Why is hard to design using clock-less circuits for larger problems? Can you give an example of a hardship? \$\endgroup\$– DebbieCommented May 1, 2020 at 23:41
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Using a clock allows us to build synchronous logic, ultimately letting us accurately control the timing and sequence of the operations that our circuits perform. On each clock transition, all of our storage elements update on that edge, meaning that our circuit makes one state transition to the next state. This is a very important simplifying factor for our design, since the transitions are all synchronized and predictable. We need to verify that our circuit meets a set of timing constraints (i.e. setup/hold times for our storage elements), and once those conditions are met, we are assured that the circuit will operate as expected. Many of our design tools (simulators, FPGA fitters, etc) are based around synchronous methodology for these exact reasons.
On the other hand, clock-less, or asynchronous circuits, make sense for simple logic problems but become extremely unwieldy and hard to design for larger problems; the assertion that clockless designs are simpler is not really true. Without a single synchronizing clock signal, different parts of the logic might operate at different speeds due to their propagation delays, which causes design challenges such as glitches, timing skews, and so on. As an illustration, an asynchronous design may requires multiple special transitions to sychronize two components, while a synchronous design with a shared clock can simply use the clock edge (and possibly a single signal, asserted synchronously with the clock).
In practice, there are asynchronous CPUs out there as an example of async design, but they are far from the mainstream; not only do they fail to fit with the more common synchronous design methodology, but many of the optimizations designed for higher CPU performance (such as the Tomasulo algorithm and other superscalar designs) assume that there is a clock that governs the time available for execution units to perform their computation and yield a value.
They achieve modestly higher performance, but the design time (and thus cost) as well as complexity of integration make them unattractive for most commercial applications.
