Regarding the RL circuit: Notice the spikes in the inductor voltage are aligned with the rise/fall times of the source voltage. With inductor voltage equal to L(di/dt), we can conclude there is a substantial di/dt from the rapid dv/dt of the input source voltage during the brief rise/fall intervals, causing these briefs periods of substantial positive/negative voltage across the inductor. Also note that the voltage remains slightly positive after the spike for positive input voltage (likewise, slightly negative after the spike for negative input voltage). We can credit this to the ESR of the inductor, which has a voltage drop from the current in the circuit.
Regarding the RC circuit: This unfortunately appears to defy our expectation, given what we know of the circuit from your question. We expect an exponential charge of the capacitor voltage of the form:
vc(t) = Vsource*(1-exp(t/RC))
which occurs after each inversion of the source voltage polarity (see image below). This time to charge ought to increase when you increase the resistance of the pot. You may consider making a second attempt at this test and check for any errors. Best of luck!