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This datasheet has a table (see Table 3-2) detailing latencies for the two parts of a 10GB Ethernet PHY, namely the PCS (Physical Coding Sublayer) and PMA (Physical Medium Attachment Sublayer).

While the latency for the PCS is unambiguously defined in clock cycles (for a clock running at 156.25 MHz), the latency for the PMA is given in "UI" (Unit Interval, I assume).

What is the UI in this context? Is it different from a clock cycle?

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The UI would be the inverse of the baud rate on the serial side of the serializer/deserializer blocks. In other words, 1/10.3125 Gbps, or 97 ps.

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  • \$\begingroup\$ Thanks! Glad to know it's so small. As a side question, do you think the 10.3125 Gpbs serial is implemented using a 10.3125 GHz clock? \$\endgroup\$
    – Randomblue
    Commented Dec 3, 2012 at 13:47
  • \$\begingroup\$ I'm not intimately familiar with the Altera SERDES modules, but I believe the PLL that generates the baud clock is internal to the module, locked to the word clock (156.25 MHz) that you provide. If multiple lanes are in use, clock generation -- and clock recovery on the receive side -- are done independently on each lane. \$\endgroup\$
    – Dave Tweed
    Commented Dec 3, 2012 at 16:44

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