How to pack oddly sized chunks of data into 128-bit FIFO

Question

In my FPGA project we get a 100-bit wide vector on each 100 MHz clock cycle from a 10Gbps receiver. I can then compress it to 75-bit wide vector due to some particulars of the data.

I would like to pack this 75-bit data into some power-of-2 chunk so that it can be transferred on the USB FIFO (32-bit) or DDR memory FIFO (128-bit) with the best throughput.

My attempt: Assume packing into 125 bits is "good enough". So the input is 3x25 wide, and the output is 5x25 wide. So on each cycle, 3 chunks are fed into a big shift register where new chunks come in on the right, and old chunks are being shifted left. Then the output selects 5 chunks at the appropriate offset. Sometimes it has to skip a cycle until enough chunks are present. The shift register is sized so that it can fit all the combinations of offsets that have to be selected.

So my question is basically, is this a common problem in FPGA designs? Does it have a name and a "proper" way to do it? Is there a generic way of solving this for all input and output sizes? Is there something obvious I'm missing where I don't have to waste 3 bits?

Answer 1

I think the term for this is a "gearbox". They are used all the time when interfacing with serializers - converting between 66 and 64 bits, 66 and 16 bits, etc. Not sure about the proper way to do it aside from whatever gets the job done, although there may be more efficient techniques that I'm not currently aware of. Personally, I wouldn't worry too much about wasting 3 bits. It's a trade-off in logic complexity. To use those 3 bits, you would probably have to implement a rather large barrel shifter, which consumes a lot of logic resources. Another concern may be what's on the other end of the link, perhaps wasting a few bits as zero padding could be an advantage so you don't have to barrel-shift again when pulling things out of the FIFO.