I want to implement some kind of event counter in my FPGA design (Vendor-A or Vendor-X). I have several dozens of signals: half are 1-bit and other half of them is 5-bit. Signals are located in different parts of my design.
I want to count summation of every signals at the same time. Signal will come at high frequency, sum of every signal should be written in 48- or 64-bit register or memory. There is no much free space in my FPGA and I want not to use full 64-bit wide adder, but find some more compact (in number of LUTs required).
How should I design my adder to be more compact? Should I split it into small fast-counting counter (of 8, 12 or 16 bits) and slow and compact serial adder for remaining bits, which will use carry from small counter? Small counter will send carry not too often, so I will have hundreds of ticks to work on wider parts in multicycle adder. Can I use one serial adders with several different small counters?