While wrapping my head around NOR gate, I found it difficult understand. Not in terms of the logic, but how it works from electrical perspective. I always like to see electrical current as water stream in a river. When you have water in the river, let's call it 1. If there's no water, let's call it a 0. It's fairly easy to understand that you can block the flow to make 1 to become 0 with a gate. But how exactly does it work when it's coming from turning two zeros into a one? It seems odd to me that you can turn two of "nothing" and output "something". When two low voltage as zero digital signal turn into a high voltage one, where's the energy coming from?
3
-
1\$\begingroup\$ The energy comes from the supply pins that must always be connected to a source of power. In a common logic family known as CMOS, the two inputs are voltages, which turn transistors inside the chip on and off. Those transistors connect the output to the positive rail to output a 1 when both inputs are zero, and otherwise connect the output to the negative rail to output a zero. \$\endgroup\$– nanofaradCommented May 11, 2021 at 18:41
-
1\$\begingroup\$ Maybe the source of your confusion is that we don’t show the power supply in logic diagrams, just the gate symbols. But the logic diagram is only meant to show the flow of data, not power. \$\endgroup\$– MartinCommented May 11, 2021 at 19:55
-
\$\begingroup\$ The water analogy only goes so far. You could think of it like a switch. A high and gate is a source of water. A low and gate is a sink for water. That's if you want to want to stay within your water analogy. \$\endgroup\$– StainlessSteelRatCommented May 11, 2021 at 21:20
Add a comment
|
1 Answer
\$\begingroup\$
\$\endgroup\$
When two low voltage as zero digital signal turn into a high voltage one, where's the energy coming from?
It's coming from the power supply. A practical gate will have a power supply.
Here is the schematic of a CD4001B buffered NOR gate.
When the output is high, the p-channel MOSFET at the output is 'on', so current can flow from Vdd to the output pin.
Here (even simpler) is the old unbuffered version (all four gates) so only 4 transistors each. Photo from McMOS Databook First Edition:
(and, yes, there are some shorts in there!) Pretty bad schematic, in fact.
answered May 11, 2021 at 18:40