When the VTC curve shifts to the left for a CMOS inverter.
why is that the delay for both Tphl and Tplh both increases?
What's the reason behind it and what is the quantitative explanation?
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2\$\begingroup\$ explain what you think changes with delay . Is it the slope or the threshold, neither or is it RdsOn and load + Miller capacitance? \$\endgroup\$– D.A.S.Commented Nov 2, 2021 at 5:50
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\$\begingroup\$ delay increases with capacitance, but the change in VTC curve seems irrelevent? \$\endgroup\$– uri leidsCommented Nov 2, 2021 at 7:44
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2\$\begingroup\$ I’m voting to close this question because this looks like a homework question. It is OK to ask about homework but you have to show what you did to answer the question. You show nothing. Also those curves are unclear, are you plotting monkeys vs bananas? Or voltage over time?? Or voltage over voltage? Always clearly indicate what is plotted versus what, assume that no one knows what a "VTC curve" is (which I don't, I can assume but I you to make clear what it is). \$\endgroup\$– BimpelrekkieCommented Nov 2, 2021 at 8:53
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1\$\begingroup\$ Vt is Vgs(th) so VtC is the transfer function vs Vout with CMOS. But no effort Pity. If it shifts what would cause that? and how are they related? explain this in your question. Iwon't vote to close you, but will you try harder? \$\endgroup\$– D.A.S.Commented Nov 2, 2021 at 11:09
1 Answer
The VTC curve will shift to left when the driving strength of NMOS is greater than PMOS, which can be made by increasing W/L of NMOS. Conversely, this can also be done by decreasing driving strength of PMOS. I have done some spice simulations and found that Tplh increases when the VTC shifts to left and Tphl decreases for the same. This can be explained by the fact that since (W/L)n is now higher, therefore it can easily discharge output in lesser time, while making it difficult to charge , thus increasing tplh.
Results:
Tplh = 14ps for W = 300n
Tplh = 17ps for W = 800n
Tphl = 15.8ps for W = 300n
Tphl = 7.3ps for W = 800n
Hope it helps