You should generally have about half the layers in the design,
dedicated to planes. You can use fewer at higher layer counts, when
modest crosstalk is not an issue (e.g., most digital comms, but not
precision RF).
So, for a 4-layer board, since the outer layers have stuff placed on
them (assuming a typical mostly-SMT design), you won't get much
coverage there, so inner layers it is. And there are two inner
layers, so you can do GND and one VCC (divided up between domains
however you like).
For a 2-layer board, you can only afford one.
But it's worse than that, because even if you have single sided
placement (all components on top), you inevitably must resolve
crossings by switching traces to the bottom side, for at least a short
length. This creates a slot in the bottom pour.
And if we pour on top, we'll have even less density due to all the
components and routing already there.
So what to do?
If we pour both, and add stitching vias between top and bottom, around
any crossing, or around any span where there's a slot in the
respective layers, and avoid routing on both layers in a given
location as much as possible: we can keep the loop length to a
minimum. That is, the loop of ground surrounding any given point, on
any given route.
We can make an observation: anywhere two traces cross (or a trace
under a row of component pads, etc.), there is a void straight through
both pours. The negative space in both, is overlapping. In the case
of two traces crossing, the best we can do is three or four vias in
the corners beside the intersection, keeping the loop size down to
trace width + 2*clearance. We should strive to minimize this loop
area.
If we poured VCC and GND, we would find we inevitably need numerous
connections (jumper traces) to both, from pins orphaned by other
connections. The impedance, from any given point to this combined
reference plane, will be higher. Bypass is easy enough at least, caps
can be placed anywhere the two pours overlap -- but getting to them is
the problem, and to get low impedance at a component, you're probably
still going to need local bypass anyway. (One of the advantages of 2+
planes, is being able to eliminate some bypass caps. Appnotes try to
play it safe, they won't recommend this -- but it is very reasonable
option, when one takes the time to consider the power distribution
network (PDN).) But worst of all, we don't have an alternate layer to
stitch against: every single trace, on either layer, is a complete and
utter void in that entire plane. Ideally perhaps we would place a
bypass cap at every crossing -- but that will get obnoxious very
quickly, not to mention expensive. We should only need a bypass for
every power pin say, or group thereof. Perhaps we would stitch by
using two vias and a jumper track on the opposite layer -- but this is
very fragile, not to mention tedious. (This is a good alternative in
locations where it's the best option, but it's probably a bad idea to
design a whole board this way. Let alone maintain such a design.)
Whereas stitching vias can sometimes be handled by EDA tool alone!
So I recommend to route a 2-layer board as ground both sides, and the
layer affinity can vary with area. So, preferably most components and
routing is on the top, but bottom routing or placement is perfectly
acceptable as long as it's stitched as well as the top side placement
is; and as long as both are as exclusive as possible (no overlap).
VCC should be routed point-to-point as any other signal, with
point-of-use bypass, and other PDN considerations as applicable. (A
point-to-point chain topology will generally approximate a
lumped-equivalent transmission line network, which is easily
terminated with some resistance at one or both ends. We don't want to
draw DC current with those terminations, so an R+C is used. Typically
an electrolytic or tantalum capacitor with nominal ESR, or a ceramic
with the ESR added in series as a separate resistor.)
