I wonder what stackup people here use when designing 2-layer and 4-layer PCBs.

When I design a 2-layer PCB, I mostly use the top layer for signal and power. I put a ground pour around the signal lines to lower the impedance. I try to make the bottom layer completely ground.

I didn't work much with 4-layer PCBs. However, when designing a 4-layer PCB, I usually use 2 layers as ground. For example sig/pwr---gnd (core) sig/pwr---gnd or gnd---sig/pwr (core) sig/pwr---gnd. The purpose of making 2 ground layers is to create a close reference for the signal and power tracks.

Which stackup do you follow when designing 2-layer and 4-layer PCBs? Which one did you have less trouble with?


2 Answers 2


I like explaining it this way: https://www.eevblog.com/forum/projects/pcb-top-and-bottom-pour-gnd-and-vcc/msg3522442/#msg3522442

You should generally have about half the layers in the design, dedicated to planes. You can use fewer at higher layer counts, when modest crosstalk is not an issue (e.g., most digital comms, but not precision RF).

So, for a 4-layer board, since the outer layers have stuff placed on them (assuming a typical mostly-SMT design), you won't get much coverage there, so inner layers it is. And there are two inner layers, so you can do GND and one VCC (divided up between domains however you like).

For a 2-layer board, you can only afford one.

But it's worse than that, because even if you have single sided placement (all components on top), you inevitably must resolve crossings by switching traces to the bottom side, for at least a short length. This creates a slot in the bottom pour.

And if we pour on top, we'll have even less density due to all the components and routing already there.

So what to do?

If we pour both, and add stitching vias between top and bottom, around any crossing, or around any span where there's a slot in the respective layers, and avoid routing on both layers in a given location as much as possible: we can keep the loop length to a minimum. That is, the loop of ground surrounding any given point, on any given route.

We can make an observation: anywhere two traces cross (or a trace under a row of component pads, etc.), there is a void straight through both pours. The negative space in both, is overlapping. In the case of two traces crossing, the best we can do is three or four vias in the corners beside the intersection, keeping the loop size down to trace width + 2*clearance. We should strive to minimize this loop area.

If we poured VCC and GND, we would find we inevitably need numerous connections (jumper traces) to both, from pins orphaned by other connections. The impedance, from any given point to this combined reference plane, will be higher. Bypass is easy enough at least, caps can be placed anywhere the two pours overlap -- but getting to them is the problem, and to get low impedance at a component, you're probably still going to need local bypass anyway. (One of the advantages of 2+ planes, is being able to eliminate some bypass caps. Appnotes try to play it safe, they won't recommend this -- but it is very reasonable option, when one takes the time to consider the power distribution network (PDN).) But worst of all, we don't have an alternate layer to stitch against: every single trace, on either layer, is a complete and utter void in that entire plane. Ideally perhaps we would place a bypass cap at every crossing -- but that will get obnoxious very quickly, not to mention expensive. We should only need a bypass for every power pin say, or group thereof. Perhaps we would stitch by using two vias and a jumper track on the opposite layer -- but this is very fragile, not to mention tedious. (This is a good alternative in locations where it's the best option, but it's probably a bad idea to design a whole board this way. Let alone maintain such a design.) Whereas stitching vias can sometimes be handled by EDA tool alone!

So I recommend to route a 2-layer board as ground both sides, and the layer affinity can vary with area. So, preferably most components and routing is on the top, but bottom routing or placement is perfectly acceptable as long as it's stitched as well as the top side placement is; and as long as both are as exclusive as possible (no overlap). VCC should be routed point-to-point as any other signal, with point-of-use bypass, and other PDN considerations as applicable. (A point-to-point chain topology will generally approximate a lumped-equivalent transmission line network, which is easily terminated with some resistance at one or both ends. We don't want to draw DC current with those terminations, so an R+C is used. Typically an electrolytic or tantalum capacitor with nominal ESR, or a ceramic with the ESR added in series as a separate resistor.)

  • \$\begingroup\$ Thank you for the explanation. When designing a 4-layer PCB, I hesitate to use one of the inner layers for power and I say to myself ''I'm not routing the signal traces close enough to the ground. This makes impedance control difficult.'' And for the battery powered PCBs, I design power as traces. I'm trying not to pour. \$\endgroup\$
    – harmonica
    Commented Jul 5, 2022 at 11:37

I agree with your 4-layer approach and much for the same reasons. Everything (namely power AND signals) should be routed in close proximity to a ground plane if you care about signal integrity and EMC. This basically forces two layers to be ground planes. And it forces signal and power to share the same layers.

Routing power has never been an issue for me. I regulate and decouple it at the consumer, so the impedance of the power routing is almost irrelevant. I would take another ground plane over a power plane almost any time.

The potential exception

I have not made boards for large ASICs or FPGAs yet. Those sometimes need very low power supply impedance (below 100 mΩ) in a range up to 100 MHz and more. This is only achievable if you connect the supply capacitors via tightly coupled power-ground plane pairs. Even then, it is unlikely to reap any benefit from extending the power planes beyond the area under the IC and its decoupling capacitors.

  • \$\begingroup\$ I've done an FPGA on 4 layers, though it was a bit hairy to lay out, and probably not all that great power quality in the end. But we weren't doing anything demanding, just a mid line Cyclone 3, nothing needing low phase noise/etc., and, I think 1.2, 2.5 and 3.3V supplies, nothing extravagant. So it can be done, but it of course matters what the application is. \$\endgroup\$ Commented Jul 5, 2022 at 23:53
  • \$\begingroup\$ FYI, based on my calculations, there's very little that can be done on-board, at these kinds of impedances, for frequencies near let alone above 100MHz or so: the balls themselves have more inductance than you can bypass out at that point. Fortunately, they place wide-body or even LGA bypass caps on the chip carrier itself to manage this for you, and further with multiple power layers on the die, or simply the mass of gates themselves serving as bypass into the 10s GHz. \$\endgroup\$ Commented Jul 5, 2022 at 23:55
  • \$\begingroup\$ @TimWilliams the pinout matters a lot for these chips. But say you have 100 ball pairs of power and ground, each with a loop inductance of 1 nH. 10 pH total. Staying below this with discrete caps is hard, but easy with plane pairs. That is why I thought people used planes for decoupling at the highest frequencies. \$\endgroup\$
    – tobalt
    Commented Jul 6, 2022 at 4:19
  • \$\begingroup\$ Right, and the chip itself might be a few uF (my assumption -- what capacitance does it have, VDD to GND, anyway? good question, that's not one you see in a datasheet!), which has a cutoff with 10pH of 50MHz. That's a very hand-waving way to put it, and there will be some effect from planes and such, but it's in the right ballpark. Or likewise, you're only going to get a few uF of chip caps under the BGA. The plane helps by joining all those caps (and balls, and etc.) together as a nearly-ideal connection, so you don't have to worry as much about resonances between caps if they're equal. \$\endgroup\$ Commented Jul 6, 2022 at 4:25
  • \$\begingroup\$ @TimWilliams This document I just googled ( indico.cern.ch/event/926254/contributions/3906671/attachments/… ) puts the frequency range of on-chip decoupling to above ~100 MHz, so your estimate is pretty close. This questions my opinion about power planes for large ICs! It looks like the power plane is only really relevant in between the SMD caps and the IC pins (see slide 12), but doesn't need to extend more. So even in these cases (large ICs), dedicating whole layers to power planes appears questionable. \$\endgroup\$
    – tobalt
    Commented Jul 6, 2022 at 5:47

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