Derivation help: gain of 2 NMOS in series

Question

I am trying to find the gain (Vout/Vin) of the circuit below, this is not a real circuit that I have, I am just trying to learn more about circuit analysis. The circuit reminds me of a cascode circuit where the gates are the same potential instead of one being Common Gate.

How/where do I start to derive this?

Why is M1 in triode region?

Why is M2 in saturation region?

I did a small signal model analysis followed by short circuiting the output to ground. I followed this up with inserting a test voltage and setting vin to 0V.

Out of this, I got a gain of gm1*(ro1+ro2) . However I am not sure if this is correct. Any help is appreciated

Answer 1

As stated in my previous answer, I thought that the intrinsic gain was \$ G_{eq} = g_{m}*(r_{o1}+r_{o2}) \$.

So I tried simulating both the circuit in question with 2 identical N-mosfets and a normal N-mosfet common source amplifier. for my simulations I've used the Microcap spice simulator with the 2N7002 model for the mosfets.

First, the CS Amplifier :

I've chosen to run the simulations at the operating point : \$V_{gs}=3.5V , I_{D}=100mA\$ (Dont mind the "AC 0.1", the plots were adjusted accordingly)

For your circuit, I thought that I would see a \$+6dB\$ increase. However the gain doubled (well, in decibels..):

The gain got squared ! It went from \$ 49.3 dB \$ to \$ 98.6 dB \$. This looks exactly like a cascode amplifier but with the \$ 180° \$ phase shift of a CS amplifier.

For a sanity check, I've simulated the equivalent cascode amplifier :

The intrinsic gain isn't the same since the operating point definition is different for each amplifier. But overall the two amplifiers behave similarly in term of gain.

Back to the drawing board

Let's try to find the Gain and Output impedance of your Amplifier with two different mosfets.

Gain :

The hybrid Pi-model for low frequencies is the following (By Krishnavedala - Own work, CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=36311653):

The amplifier then becomes (Drawn by me):

The output voltage can be written as (Implying an Ideal current source):

\begin{equation} V_{out} = V_{DS2} + V_{S2} \end{equation}

with :

\begin{equation} V_{DS2} = -g_{m2}r_{o2}(V_{in}-V_{S2}) \end{equation}

and

\begin{equation} V_{S2} = -g_{m1}r_{o1}V_{in} \end{equation}

After substitution :

\begin{equation} V_{out} = -[g_{m1}g_{m2}r_{o1}r_{o2}+g_{m1}r_{o1}+g_{m2}r_{o2}-1]V_{in} \end{equation}

So, the intrinsic Gain can be approximated to :

\begin{equation} G = -g_{m1}g_{m2}r_{o1}r_{o2} \end{equation}

This approximation works since the gain \$ g_{m}r_{o} \$ is always higher than 20.

At this stage, we can see that \$ V_{S2} \$ is always \$ g_{m2}r_{o2} \$ times lower than \$ V_{out} \$. This might explain why M1 is in triode region.

Output Impedance : #### (In progress)

Answer 2

Why is M1 in triode region? Why is M2 in saturation region?

Start by assuming same W/L ratio for both devices. Then, if you imagine that both devices have a specific Id vs Vds curve for one specific Vgs and Ir, then each has one specific Vgs that will give Ir for the specific W/L and Vgs.

If this is true (which it is), then you can see that if vin = Vgs1 the voltage at the gate only has enough voltage to supply one full Vgs to both devices, but the M2 would have 0 volt left to supply M1 vds > 0. And M1 vds needs to be a minimum value to be saturated. So right away, M1 cannot be saturated.

M1 has a fixed Id vs Vds curve for a fixed Vgs, but M2 can adjust it's Vs, or equivalently, shift its specific Vgs curve, to get both devices to some operating point to have the same Id (via loop feedback in the circuit configuration).

Now, M1 will move backwards on it's fixed (Vgs) Id vs Vds curve until both currents equalize to a lower value and M1 moves all the way to triode, the top device M2, will adjust by shifting its Vgs (by adjusting the s value and hence Vd to M1) to give equivalent Id as this new M1 operating point in triode. So top device M2 is now is still in saturation (but on a shifted Id/Vds Vgs operating curve), and M1 is the original Id/Vds Vgs curve but operating way back in triode. You'll also notice the original expected current is no longer the same, because the current had to drop for the devices to equalize to the same current.

Answer 3

>How/where do I start to derive this?

I don't know how to derive \$ G_{eq} = g_{m}*(r_{o1}+r_{o2}) \$ from two random transistors with different characteristics.

However, if I suppose that the 2 mosfets are planar and have the same \$ W\$ and \$ L\$ (channel width and length), we can think of them as stacked-up mosfets :

(Image drawn by me)

The equivalent mosfet would have a channel length of \$ 2L\$ (approx.) and a width of \$ W\$.

The output resistance formula is :

\$ r_{o,eq} \approx \frac{1}{\lambda I_D}\$

with \$ \lambda \approx {\frac {\Delta L}{V_{E}L_{eq}}} \$

Since we have doubled the channel Length, then \$ r_{o,eq} \approx 2*r_{o} \$

Then, transconductance can be simplified as \$ g_{m,eq} \approx \sqrt{2 \mu_n C_{ox,eq} (\frac{W_{eq}}{L_{eq}}) I_D} \$

With :

• \$ L_{eq} = 2L \$
• \$ C_{ox,eq} = 2C_{ox} \$ since we doubled the area of the gate = W*2L

We can conclude that \$ g_{m,eq} \approx g_{m} \$

And thus, the 2 stacked-up mosfets would have double the Gain : \$ G_{eq} \approx 2*G \$.

Why is M1 in triode region?

Why is M2 in saturation region?

I am going to simulate this circuit during the weekend and update my post accordingly. But if it's the case, why is the gain \$ G_{eq} = g_{m1}*(r_{o1}+r_{o2}) \$ ?

Shouldn't M1 be in saturation while M2 should be in the triode region acting as a Drain resistor for M1. (According to the gain you've found)