Let's say I have a 5-bit integer frequency divider first.
Does this mean that I can divider my input frequency anywhere from 1 to 2^5 (or 2 to 2^5+1 as dividing by 1 doesn't make much sense)?
If you have a programmable divider, then yes, it can divide by any number within its programming range. For instance, a down counter could be reloaded with N every time it counts down to 0. This would then divide by N (or N-1 or N+1 depending on how you pipelined the detect-0 to reload-with-N logic).
Dividing by 1 makes perfect sense with this type of divider, it generates a reload pulse for every input pulse. This makes more sense in an FPGA where it might be generating a clock enable signal for a process that did not have to execute every clock cycle. You're right that it would make no sense if you wanted a lower frequency squarewave out.
Now let's say I have a 100 MHz input frequency signal and set a divider value of 3. Will the output be 33 MHz or 33.33 MHz?
Neither, it would be 33.3 recurring, more easily written in rational form as 100/3.
Now let's look at the 5.5 bit fractional frequency divider.
Here what does 5.5 mean? I read somewhere(but not sure of the source) that a x.y fractional divider means x bits for the integer part of division of y bits for the fractional part. What does this mean exactly? What value will I be dividing my input frequency by exactly?
A divide by 5.5 (decimal, five and a half) would be done by having a divider that divided by 5 for one output cycle, then 6 for the next. That way, you would have two output cycles for every 11 input cycles. This can be generalised to any value of modulus.
If you are using 5.5 notation to mean 5 integer and 5 fractional binary bits, then you would have a 5 bit binary divider, whose division ratio could be altered every cycle, in a sequence of either exactly 32 cycles, or up to 32 cycles, depending on whether the fractional modulus was programmable.
Typically, a fractional divider only makes sense when doing frequency synthesis.
To get low noise synthesis, you need a high reference frequency. The resolution of a conventional integer divider digital PLL is always a multiple of the reference frequency, which might be inconveniently high for your application.
Fractional synthesis creates unwanted sidebands at the longest divider sequence repeat. The 11/2 divider would have sidebands at half the reference frequency.
When a fractional divider is used with a small modulus to get lower phase/multiplication noise, then usually these sidebands can be arranged to be outside the loop bandwidth, and so filtered out. For instance, if you wanted 1kHz resolution, with a 10 kHz reference, then you could use a fractional divider with a modulus of 10, and filter the 1 kHz sidebands out with a loop filter of 100 Hz bandwidth or less.
When a fractional divider is used with a large modulus to get fine resolution, it's no longer possible to filter out the sidebands. They could be cancelled, a process that is now largely obsolete, using DACs to inject cancelling signals into the PLL. More common today is to use noise shaping to move the energy up to high frequencies where it can be filtered out by the loop filter. This involves using more ratios than we would expect, and requires the PLL and phase detector to be exceptionally linear, to avoid distortion down-converting this shifted energy back down into the loop.
What is the difference between an integer frequency divider and a fractional frequency divider?
To answer specifically the question of your title - an integer frequency divider divides by the same count every output cycle. A fractional divider selects a new count value every output cycle, according to some algorithm.
