Hold Step (pedestal) in a sample and hold circuit

Question

I just read the Specifications and Architectures of Sample-and-Hold Amplifiers from TI as part of my studys for sample and hold circuits. On page three it says the following:

Hold Step, also known as pedestal and sample-to-hold offset, is the voltage step that appears at the output due to the sample-to-hold transition (Figure 4). It is caused by a transfer of charge to the hold capacitor due to the opening of the switch.

I don't really understand how a charge transfer takes place here. I assume that the switch has a parasitic capacitance across the switching path, but how does that then increase the voltage at the ouput?

Answer 1

You can easily simulate this. Consider this simplistic sample and hold circuit: -

The waveforms would typically look like these: -

Then, if you looked closely at the output waveform when the sample pulse falls to zero (indicating the start of the hold period) you would see this: -

I don't really understand how a charge transfer takes place here. I assume that the switch has a parasitic capacitance across the switching path, but how does that then increase the voltage at the output?

It's not the parasitic capacitance across the switching path but, the parasitic capacitance between the control pin and the output pin. In my circuit above I show it as 1 pF. If this rose to 10 pF, the disturbance would be clearer: -

Note that I've doubled the Y-scale to fully accommodate the much bigger disturbance. But you may ask why the glitch I have shown is negative (and not positive as shown in the TI document) and this is all down to the implementation of the sample and hold circuit. For instance, I could change my simulation circuit to this: -

And now, if I look at the output waveform in fine detail I would see a positive transition when the circuit enters the hold-phase: -

Answer 2

I don't really understand how a charge transfer takes place here. I assume that the switch has a parasitic capacitance across the switching path, but how does that then increase the voltage at the output?

The schematic below represents the sample-&-hold circuit of that app note referenced in the question. At time t=0 the switch is connecting M1 gate to 0V (GND). Thus M1 is ON, and Vh matches Vin. M1 gate-to-drain parasitic capacitance is charged; with drain at Vh (positive), and gate at 0V. I have drawn a discrete capacitor here to demonstrate this parasitic capacitance between gate and drain, refer Cgd. Cgd is charged, top terminal is at Vh=Vin (positive), bottom terminal is at 0V.

^{simulate this circuit – Schematic created using CircuitLab}

Sometime later when t=Ts, the switch changes state to turn off Q1. This raises the gate to the same potential as Vin (M1 source terminal), but makes Vgs = 0V which turns off M1. However, this also means the bottom terminal of Cgd is now at Vin. The charge that was on Cgd has to go somewhere, where does it go? Some of it goes to the source terminal through the MOSFET, and some of it must go into C1, thus increasing Vh.