Can generated events get placed before events already in the event queue in SystemVerilog?

Question

I tried to consult the Verilog LRM but wasn't successful; some of the reason is because I don't really know the correct terminology. This question is related to this one here, but I never got an answer that answered this part of the question.

In short: is it possible according to Verilog LRM for events generated (because of event-controlled evaluation) after some other event to be executed BEFORE an event already in the active region of the event queue?

For example, in the code below, can b get updated before a? Assume that the relevant declarations for the given signals have been given elsewhere.

always begin
clock = 0;
clock = 1;
#1;
end

always begin
a = 1;
end

always @(posedge clock) begin
b = 1;
end

My suspicion would be that the simulator schedules a's update before it knows that b will update at all (since it's not yet executed the clock rising), so that when b's evaluation and update events get generated these are appended behind the corresponding events for a. But is this mandated by Verilog? See the link above for another example of this situation.

Answer 1

The LRM section 4.7 Nondeterminism basically says that event regions are not queues--events scheduled in the region may be executed in any order.

Your example is degenerate because the order your always block execute can produce many different results. If the second always block executes first, the simulation will hang. The third always block must execute before the first to ever see the posedge of clock. A better example is this mix of procedural assignments and continuous assignments.

always @(posedge clk) begin
    data1 = in;
    data2 = plus_data;
end
assign plus_data = data1 + 1;

Some optimizations inline the continuous assignemnt so that plus_data already has the updated value. That makes it appear that the scheduler executed the continuous assignment first even though it had not finished executing the always block.