Confusion over clocks in FPGAs / Verilog

Question

I just purchased an FPGA and I am learning Verilog but I have run into a few confusions, most of them regarding the clock.

My first question is, how does sequential logic work? Are the assignments made, one per clock cycle, or does the sequencing somehow propagate at maximum speed, determined by gate delays?

My second question is, how do frequency multipliers work? I saw an article which used one to get a 250MHz signal on a chip clocked at only 50MHz. How is that possible? If the chip is capable of operating at such higher frequencies (limited only by gate delays I would presume), then why isn't the chip just clocked at a higher frequency to begin with?

How does combinational logic in an always block work? I thought always blocks were executed on events, like positive or negative signal edges, and ran sequentially, so I am fairly confused on this point, as I have seen blocking assignments inside always blocks.

Answer 1

First of all, throw out this concept of 'instructions'. They do not exist in Verilog. Nothing is executed. Verilog, VHDL, SystemVerilog, etc. are what are called hardware description languages. They are not executed. They are not interpreted. They define hardware components (logic gates, flip flops, registers, etc.) and their interconnections. (Not entirely accurate I suppose; but the only verilog that you can put on an FPGA - synthesizable verilog - will not be executed or interpreted. Testbenches are a different animal.)

Clocks are used to drive flip flops and registers. Data can be shifted into flip flops and registers on the edges of the clock. So inside of an always @(posedge clk) block, all of the statements will be 'executed' simultaneously and the results will be latched into the registers on the clock edge, according to the rules of how the HDL statements are interpreted. Be very careful where you are using = and <=, though. The meaning of these two assignment operations is very different inside of an always block. The basic idea is that all of the = operations are dealt with first in order of appearance. This happens at the propagation speed of the gates. Then all of the <= are dealt with at the same time, storing the argument into a register. The only thing the clock affects in this case is precisely when the registers are updated. If you are running a simulation, it won't matter how many operations need to occur between registers, but on an FPGA the clock will have to be slow enough to ensure that any changes have been able to propagate through the logic.

Faster clocks can be generated using a device called a phased lock loop (PLL). PLLs are not synthesizeable in verilog, but generally there is a way to instantiate a dedicated PLL component on the FPGA you are using. Actually, I take that back, you can certainly make a digital PLL in verilog, but you can only use it to generate signals lower than the clock frequency. A PLL contains a voltage controlled oscillator, one or more frequency dividers, a phase comparator, and some control circuitry. The output of the VCO is divided down and phase compared with the input frequency. The VCO control voltage is adjusted until the divided down VCO output precisely matches the frequency and phase of the reference signal. If you set the divider to 5 and use 50 MHz for the reference frequency, the PLL will generate a 250 MHz signal that is precisely phase locked to the 50 MHz reference. There are several reasons for doing this. Using a PLL allows generation of multiple clocks so different logic can be run at different speeds e.g. for specific peripheral interfaces or for slow, complex combinatorial logic. It also can allow the device to control its own clock frequency to save power.

Blocking statements inside of always blocks will generate combinatorial logic. Again, this logic will generally always be 'executed' regarless of the clock because it defines actual logic gates. It can be beneficial to use a few temporary variables, but care must be taken to ensure that there isn't so much extra logic that the timing requirements are not met.

Answer 2

1. Both are possible, and usually called asynchronous versus synchronous logic. You may want to look a bit deeper into this, especially since you can at least describe various synchronoaus schemes (e.g. trigger on level or edge). Maximum reliability is often achieved with edge-triggering, because of race conditions with level-triggering. Hence FPGAa tens to bw optimized fr that.

2. Using a PLL. Most designs use multiple clocks, and the limit comes from what kind of circuit you synthesize. For proper edge-triggered synchronous designs, the synthesizer may already calculate it for you (and for everything else you may have to learn to manuallg supress warnings or errors about its inability to do so).

3. See this question.