Understanding the Verilog Stratified Event Queue

Question

I'm trying to understand how the Verilog scheduling algorithm works. The below example outputs 0, xxxx and not 1010. I'm not clear why. If I do put a delay before $display, it would output 1010.

module test;
  reg [3:0] t_var;
  initial begin
    t_var <= 4'b1010;
    $display("%0t, %b", $realtime, t_var);
  end
endmodule

Same output, 0, xxxx, for the below example:

module test;
  reg [3:0] t_var;
  wire [3:0] y;
  assign y = ~t_var;
  initial begin
    t_var = 4'b1010;
    $display("%0t, %b, %b", $realtime, t_var, y);
  end
endmodule

Based on the examples, it looks like that both nonblocking assignment and continuous assignment are two-step processes where the RHS is evaluated at the current time step and the LHS is scheduled to happen at the next time step (if no delay is specified) or at a later time step (if a delay is specified).

Can someone please confirm or explain to me a step-by-step flow of the algorithm below (from Clifford Cummings) as it applies to the examples above?

Thanks!

Answer 1

You are correct in saying that the non-blocking assignment(NBA) and continuous assignment(CA) act like two-step processes, because they are. The problem is what you are calling "the next time-step" is not an advance in time; it is an iteration of the while() loop without advancing time. This is usually referred to as a delta-step.

When using an NBA, the LHS gets scheduled as an NBA update event, but right after that, the $display is the next active event to execute. It prints the value of y before the NBA update events have a chance to execute. As soon as you introduce a delay, the NBA has a chance to execute before advancing to the next event time.

When using a CA, you are creating a separate process that activates anytime the RHS changes it makes an assignment to the LHS in the same active region. The initial and CA are two independent processes, and the ordering between statements in the active region is non-deterministic. So whether you see the old uninitialized value of y of updated value of y is a race condition. And you will see differences between simulators depending on how they optimize this code.