Timings constrains for isochronous clocks

Question

In my Verilog design, I have two clocks of the same frequency, but of different phase. At the moment, my timing constraints look like this:

create_clock -name clk1 -period "150 MHz" [get_ports clk1]
create_clock -name clk2 -period "150 MHz" [get_ports clk2]

The problem is that the compiler doesn't complain when signals cross the two time domains, although it should because the two clocks are asynchronous, and metastability protection is required.

The "hack" of changing one of the frequencies to 150.01 Mhz works, but it's a hack. Is there a proper way of setting timing constraints for isochronous clocks?

Edit: I'm using Altera Quartus II as my compiler.

Answer 1

Put clocks in different clock groups. This allows them to have the same phase and frequency yet be considered asynchronous for timing analysis. For a Quartus II .sdc file you would use this syntax:

create_clock -period "100 Mhz" -name {CONF_CLK}  [get_ports {CONF_CLK}]
create_clock -period "100 Mhz" -name {PCIE_CLK} [get_ports {PCIE_CLK}]
create_clock -period "645 Mhz" -name {GXB_REFCLK} [get_ports {GXB_REFCLK}]

# Specify clocks are unrelated by assinging to seperate asynchronus groups
set_clock_groups -asynchronous -group {CONF_CLK} -group {PCIE_CLK} -group {GXB_REFCLK}

And yes, -period can be either a frequency or time period, depending on the units specified.

Answer 2

You can use -phase with create_generated_clock. For example, below are two 125.0 MHz clocks, but the second one is shifted 90 degree:

create_generated_clock                                                  \
    -source {pll0|altpll_component|auto_generated|pll1|inclk[0]}        \
    -divide_by 4 -multiply_by 5 -duty_cycle 50.00                       \
    -name clk_125                                                       \
    {pll0|altpll_component|auto_generated|pll1|clk[0]}

create_generated_clock                                                  \
    -source {pll0|altpll_component|auto_generated|pll1|inclk[0]}        \
    -divide_by 4 -multiply_by 5 -phase 90.00 -duty_cycle 50.00          \
    -name clk_125_90                                                    \
    {pll0|altpll_component|auto_generated|pll1|clk[2]}

Answer 3

The tool assumes that clocks are rising-edge aligned, I believe, unless you otherwise specify them. That's why the tool doesn't complain.