I am trying to write a testbench for a 16-bit RISC processor using verilog in Xilinx. I have the following modules:


My question is : To get this to work do i need to create just one test bench for the 'TOP' module and have '$display' statements for each module inside it?

FOR EXAMPLE, if i have to display output of the alu module then should I have the display statement in the test bench for TOP?

module top_test;

    // Inputs
    reg clk;
    reg rst;
    reg start;

    // Outputs
    wire [4:0] PS;
    wire [3:0] opcode;
    wire [15:0] PC;
    wire [15:0] IM_instr;
    wire [15:0] IR_instr;
    wire [14:0] CV;
    wire [15:0] R1_reg;
    wire [15:0] R2_reg;
    wire [15:0] R3_reg;
    wire [15:0] R4_reg;
    wire [15:0] R5_reg;
    wire [15:0] R6_reg;
    wire [15:0] R7_reg;
    wire [15:0] R8_reg;
    wire Z;
    wire [15:0] A_ALU;
    wire [15:0] B_ALU;

    // Instantiate the Unit Under Test (UUT)
    TOP uut (

    initial begin
        // Initialize Inputs
        clk = 0;
        rst = 0;
        start = 0;

        // Wait 100 ns for global reset to finish

    #100 ;
    rst = 1;

//  $display($time, " alumod A_in=%b,B_in=%b,ALU_out=%b", A_in, B_in, ALU_out); 

          #5 clk = !clk;


alu module code :

module alumod(clk,rst,load_SR,ALU_opcode,A_in,B_in,ALU_out,data,carry,Z);

    input clk,rst;
    input [15:0] A_in,B_in;
   input [2:0]  ALU_opcode;
    input load_SR;

   output [16:0] ALU_out;
    output [15:0] data;
    output carry, Z;

   reg [16:0] ALU_out;
    reg Z;

    always@(ALU_opcode or A_in or B_in)


    3'b000:  ALU_out = A_in + B_in;
    3'b001:  ALU_out = A_in - B_in;
    3'b010:  ALU_out = {{16{A_in[15]}},A_in} >> B_in; //ARITHMETIC 
    3'b011:  ALU_out = A_in << B_in;            //LOGICAL LEFT SHIFT
    3'b100:  ALU_out = A_in >> B_in;            //LOGICAL RIGHT SHIFT
    3'b101: if (A_in < B_in)                                    //SLT
                    ALU_out = 1;
                    ALU_out = 0;
   3'b110:  ALU_out = ~A_in;                    //INV

    //default: alu_out = ;

always@(posedge clk or posedge rst)
            Z <= 1'b0;
        else if(load_SR)
            Z <= (data == 0);
            Z <= Z;

        assign data =  ALU_out[15:0];
        assign carry =  ALU_out[16];

  • \$\begingroup\$ $display($time, " alumod A_in=%b,B_in=%b,ALU_out=%b", A_in, B_in, ALU_out); why you are using ALU_out in the top_test module? it's not declared there. you have to put '$display' inside the module if the pin isn't in the scope of top_test \$\endgroup\$
    – hassansin
    Commented May 3, 2014 at 7:31
  • \$\begingroup\$ I made the necessary change and put the '$display' inside the modules. But this the output i am getting: ` 0 alumod A_in=xxxxxxxxxxxxxxxx,B_in=xxxxxxxxxxxxxxxx,ALU_out=xxxxxxxxxxxxxxxxx` Why am i not getting the output? Is something wrong with the logic i have used in alumod? \$\endgroup\$ Commented May 3, 2014 at 17:38
  • \$\begingroup\$ In the testbench I don't see any test input values. \$\endgroup\$
    – hassansin
    Commented May 4, 2014 at 0:22
  • \$\begingroup\$ @ hassansin That is what I am confused about. As you can see, the top module inputs are just clk,rst and start. So the only inputs i can give to test are rst and start, right? But i dont understand how it will connect to the modules below it and give the out. \$\endgroup\$ Commented May 4, 2014 at 1:07
  • \$\begingroup\$ @ hassansin Top module code: ` module TOP(clk,rst,start,PS,opcode,PC,IM_instr,IR_instr,CV,R1_reg,R2_reg,R3_reg,R4_reg,R5_reg,R6_reg,R7_reg,R8_reg,Z,A_ALU,B_ALU); input clk,rst,start; output [3:0] opcode; output [4:0] PS; output [15:0] R1_reg,R2_reg,R3_reg,R4_reg,R5_reg,R6_reg,R7_reg,R8_reg,A_ALU,B_ALU; output [15:0] PC; output [15:0] IM_instr; output [15:0] IR_instr; output [14:0] CV; output Z; wire [3:0] opcode; wire [14:0] CV; wire Z; ` \$\endgroup\$ Commented May 4, 2014 at 1:12

1 Answer 1


I made the necessary change and put the '$display' inside the modules. But this the output i am getting: 0 alumod A_in=xxxxxxxxxxxxxxxx, B_in=xxxxxxxxxxxxxxxx, ALU_out=xxxxxxxxxxxxxxxxx Why am i not getting the output?

because you haven't provided any test input values. For example, in your testbench A_ALU and B_ALU aren't initialized. Since nets that are driven get the default value of 'x', you are getting A_in & B_in as x's.

I've simplified your code here. See the testbench code where A_ALU & B_ALU values are provided. The '$display' is used in the 'alumod.sv' file. After simulating you'll get output like this:

#                  100 alumod A_in=x, B_in=x, ALU_out=x
#                  105 alumod A_in=1010, B_in=1010, ALU_out=10100
#                  110 alumod A_in=1010, B_in=10100, ALU_out=11110
#                  115 alumod A_in=1010, B_in=11110, ALU_out=101000
#                  120 alumod A_in=1010, B_in=101, ALU_out=101
#                  125 alumod A_in=1010, B_in=100, ALU_out=110

See, for 1st 100ns the values are x since they aren't initialzed yet.

  • \$\begingroup\$ So, the testbench you have added is for just the alu module correct? But my question is, how does the testbench for 'TOP' module work? Because according to my project is about a 16 bit RISC processor and the 'TOP' module contains the data path unit and control unit. I have added the code of 'TOP' module and test bench for the same here [link](edaplayground.com/x/2mV} \$\endgroup\$ Commented May 5, 2014 at 4:26
  • \$\begingroup\$ I don't really get your question. May be it would be better if you add code for other units and simulate the testbench. \$\endgroup\$
    – hassansin
    Commented May 5, 2014 at 6:23
  • \$\begingroup\$ Yes i have link \$\endgroup\$ Commented May 5, 2014 at 21:46
  • \$\begingroup\$ updated the code. Can't simulate, 3 modules are missing. Anyway, to test TOP module, you instantiate it in testbench and put some test values for all the inputs of TOP module. Similarly if you want to test only alu module, only instantiate that module in testbench and put some test values for that module. I hope it makes sense. \$\endgroup\$
    – hassansin
    Commented May 7, 2014 at 1:04

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