I have the following code:

module one_second(OUT,clk);

output reg [3:0]OUT;
input clk; 

always @(posedge (clk))
    OUT<=4'b1110; //LINE 1
    OUT<=4'b1101; //LINE 2
    OUT<=4'b1011; //LINE 3
    OUT<=4'b0111; //LINE 4

I want the variable "OUT" to have different values from LINE 1- LINE 4 one by one after each clock pulse. After the 4th pulse it should repeat again.

  • 1
    \$\begingroup\$ Please clarify your specific problem or provide additional details to highlight exactly what you need. As it's currently written, it's hard to tell exactly what you're asking. \$\endgroup\$
    – Community Bot
    Commented Sep 27, 2021 at 14:39

1 Answer 1


You need to write a state machine, which changes its state at every clock edge. The current state defines the output. This is one of the very fundamental methods in digital hardware design, so you'll find hundreds of guides that tell you how to write a state machine in verilog.

However, in your case, the output progression can be coded more simple by figuring out how to do a circular left shift in Verilog. Since this is just applying basic verilog operators, I don't think giving you an answer how to do that here helps you very much – you'll need to apply it to you code yourself. Here the idea:

NEXT <= (LAST<<1) | LAST[3]

Note that you still need something to set the initial state.


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