Quick answer - a FET is not a bipolar transistor.
Vth relates to the minimum voltage present between Gate and Source: Vgs(threshold) if you like. The voltage present at the source will depend on the resistance between source and drain for that particular Vgs.
For an N FET, the diagram you have will not work. If the Source voltage approached the Drain voltage and the Gate voltage is also the Drain voltage, then Vgs -> 0. You need a P FET and you need the Gate to be closer to 0V.
Edit: This was an overly hasty answer patched with edits but I'll leave them as they are as Roger's comments on my answer and edits hold more value. The edits I made are:
1) Roger C's answer assumes something I didn't - that the voltage on the right (Vdd - Vth) is being held at that potential by an external reference. In that case, the illustration is correct (the maximum possible voltage at the source is VDD-Vth, otherwise the NMOS would be OFF).
2) The OP said "The picture suggests, irrespective of what the drain voltage is, the voltage at the source is always the gate voltage minus Vth". Your understanding of cause and effect is backwards: The voltage at the gate must be the voltage at the source plus a minimum of Vth in order for the NFET to be on.