When I read that the conversion clock of an ADC is for example 2 MHz. Does it mean that the ADC perform the analog to digital conversion of n-bit every T=1/2MHZ=0.5 micro second?
This is what is written in the text: With a 2-MHz conversion clock, the ADC can perform an 8-bit single conversion in 6 μs or a 10-bit single conversion in 7 μs.
I do not understand how these micro second times are derived.
In the case of a successive approximation converter, it will perform one conversion step per clock cycle, which actually performs one bit of the conversion. Thus an 8-bit conversion takes at least 8 clock cycles ( 4 us) and a 10-bit conversion takes at least 10 cycles (5 us) with a 2 MHz conversion clock (0.5 us period)
In the first step it performs the MSB conversion, asking "is the value more than half the reference voltage?", setting the MSB to '1' if yes, and subtracting either half the reference or zero (accordingly) from the input value.
In the next step it converts the next bit, asking "is the remaining value more than 1/4 the reference voltage?" and so on for each bit.
There is also some overhead, for tasks like storing the final result from the conversion into the output register, resetting the internal circuitry, and "freezing" the analog value for the next conversion (in a "sample and hold" circuit) to keep it stable during the actual conversion.
The designers of you example converter apparently decided to use 4 additional clock cycles for these tasks, thus giving 6us and 7us total time for a conversion.
There are ADCs which can perform an entire conversion in a single clock cycle, these are known as "flash" converters.
It depends on the type of ADC. For a flash ADC, you will get one sample per ADC clock cycle with a latency of one clock cycle. However, flash ADCs are rather specialized and expensive. More than likely you have a successive approximation or pipelined ADC. In both of these, one ADC clock cycle is required per bit. However, in a pipelined ADC, multiple samples will be converted at the same time, so you still get one sample per clock, but you have a latency of one cycle per bit. The ADC that you have is probably a successive approximation ADC, which is the slowest of these three types. Generally a SAR ADC works by sampling the input for several cycles, then converting it with one cycle per bit. So it may take 12 or 14 cycles to convert 10 bits with a sampling time of 2 or 4 cycles and a conversion time of 10 cycles.
This sounds as if the conversion clock is used for each bit of the conversion.
It appears that 12 clock cycles are required for an 8 bit conversion and 14 clock cycles for a 10 bit conversion.
This means that the conversion needs 1 clock per conversion bit plus an overhead (for sample time and register setup perhaps) of 4 clock cycles.
If you identify the ADC I could be more specific.
Update: Useful link
There is an excellent application note from Freescale on this module, which is used in a number of their microcontrollers. You will find the relevant formula for this successive approximation device on page 11. The minimum time for a conversion is attained when the minimum possible number of sample clocks is specified.
Table 2 has more details of how the timings are broken down.
HTH
