Many CPLD product families offer each chip in multiple packages, some of which don't bond all I/O pads out to pins. Even I/O pads which aren't bonded to pins, however, may be useful if they have bus-keeper circuits. Enable the bus keeper on a pin and it will behave as a transparent latch which samples its value whenever OE is true. In some cases, this may allow one to almost double the number of available registers (e.g. a chip with 64 macrocells could be programmed to behave as a 100-bit shift register while still having some macrocells left over). Use a few bits as a counter, have the shift register output report the state of macrocell N+2, and have macrocell N+1's output enable set while macrocell N is being latched from the data input.
Unfortunately, the only way I know of to use those extra I/O pads is to lie to the chip-design software and say I'm using the larger-footprint device, which then means all the pinouts reported by the software will be wrong for the smaller devices. Is there any clean way with e.g. a Lattice LC4064ZE-5TN48C to indicate that one is using the smaller device (so the pinouts will be correct) and yet still map functions to the pads which don't have associated pins?