Improve Quartus partial compile or recompile time

Question

I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. The rapid-recompile button is always grayed out, I don't even know what it does, I've never had the option. A lot of times, I'm not changing my design just SignalTap, but Quartus wants to recompile everything which seems like a waste of time. Is there a way speed up the compile time (or changes to only apply to SignalTap)? Using Quartus 15.1

Answer 1

Some useful flags to make Quartus synthesize faster if you don't care about fully optimizing your results and just want to get a pessimistic estimate or do comparisons.

set_global_assignment  -name PHYSICAL_SYNTHESIS_EFFORT  FAST

Specifies the amount of effort, in terms of compile time, physical synthesis should use. Fast uses less compile time but may reduce the performance gain that physical synthesis is able to achieve.

set_global_assignment  -name FITTER_EFFORT              FAST_FIT

Fast Fit decreases optimization effort to reduce compilation time, which may degrade design performance.

And instead of execute_flow -compile, use:

execute_flow -implement

Option to run compilation up to route stage and skipping all time intensive algorithms after.

In a meeting with Intel/Altera engineers, using -implement this was ball-parked to be about 20% faster than -compile, and came recommended when iterating on timing-closure results.

You could also try the following:

set_global_assignment  -name SYNTHESIS_EFFORT           FAST

Note: This has the caveat below, although I tend to see overall faster runs in some designs.

When set to Fast, some steps are omitted to accomplish synthesis more quickly; however, there may be some performance and resource cost. Altera recommends setting this option to Fast only when running an early timing estimate. Running a "fast" synthesis produces a netlist that is slightly harder for the Fitter to route, thus making the overall fitting process slower, which negates any performance increases achieved as a result of the "fast" synthesis.

Edit (Jul 21, 2020):

The below settings will punish your timing, but they can also help with compile time significantly, particularly on newer Stratix 10/Agilex designs:

set_global_assignment -name OPTIMIZATION_MODE          "AGGRESSIVE COMPILE TIME"
set_global_assignment -name ALLOW_REGISTER_RETIMING    "OFF"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD "OFF"

And you can also turn off timing analysis with the below:

set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS "OFF"

Edit 2 (March 9, 2022):

This setting is even faster than AGGRESSIVE COMPILE TIME:

set_blocal_assignment -name OPTIMIZATION_MODE          "FAST FUNCTIONAL TEST" 

This mode produces a .sof bitstream file that you can use for on-board functional testing with minimal compile time. This mode further reduces compile time beyond Aggressive Compile Time mode by limiting timing optimizations to only those for hold requirements.

Answer 2

The best/cheapest way to improve compile time is to buy a processor with more cores. Since even the free version of Quartus has multiprocessor compile capability at certain stages of the hardware compile. A new processor will run a few hundred dollars where buying the full version with the partial compile is thousands.

Do what the Java programmers do these days and ask for more hardware instead of improving software.