Balancing copper on inner layers of PCB

Question

A similar question was asked - What is Copper Thieving and why use it?

And my question originates from the comments of the answer in the linked question.

I have read and understand that to help the etching process, you balance the copper so that it effectively eats away at the board at the same rate. One of the answers/comments makes a note that its for the outer layers.

Thieving is added to the outer layers in order to help a more balanced chemical process for the plating.

What about the inner layers ?

I have a 8 layer stackup where some of the internal layers routing is not as dense as others. This is a relatively large board (15" x 8" ).

My gut/understanding tells me, that I should be balancing the copper on all layers and not just the outer layers, but I would like to be sure its needed and that my understanding is correct.

Answer 1

When a multilayer board is produced, the copper structures of inner layers and outer layers are manufactured in a different way. If an inner layer should be 35 µm thick, the take a thin board with 35 µm copper on both sides, add fotoresist, expose thru a film with the structure, develop the resist and etch all unwanted copper away.

The outer layer are done different, because the drill wholes should be plated with copper. They use a copper foil with only 17 µm for the outer layers and add another 17 µm of copper by galvanic deposition. But all areas where you want no copper are covered with resist. The galvanic deposition of copper is done only at uncovered traces and copper planes and inside the drill holes. But you want all traces to get an equal deposit of copper. If there is a single trace in an area of the board only, all copper from the galvanic anodes goes there and this trace get much more copper than only 17 µm. At other areas of the board there may be a very dense population of traces. The copper from the anodes inside the galvanic bath spreads to all traces there and the deposition of copper will be less than 17 µm.

If the outer layers are structured with a good balance, you will get an equal deposition of copper to the whole area.

Balancing the copper is recommendable only for the outer layers of the multilayer if the inner layers are structured by pure etching.

But you should ask the board manufacturer about his recommendations for inner and outer layers.

Answer 2

While the chemical process is important the primary issue with unbalanced boards are the thermal properties during production of the PCB itself.

The PCB manufacturing process involves baking the boards to cure the epoxy between layers. Copper expands more with temperature than the underlying board material (typically FR4). This means that with an unbalanced board the PCB can warp during production. I've seen some wonderfully curved pcbs that weren't flat enough to mount BGA parts to due to an unbalanced layer stackup.

Since inner layers are by definition closer to the centre of the PCB they will exert less torque on the board and so are less critical but they can still matter. Generally as long as your power planes are symmetrical you will be close enough to balanced that things will be OK. If some of your tracking layers are very bare in comparison to others then you can always consider moving some of the tracks to a different layer.

A good quality fab house will normally be able to check and warn you if they think there will be a problem with your board.

Answer 3

For sparse routing inner layers you can leave as is. There should be no need to make a big deal about those because those layers are typically just etched and then bonded to the adjacent layers without plating.

On the other hand for PWR and GND planes you want to try to fill those out to full fill. Even on split PWR planes where you may be creating islands for several different voltages you want to fill out the whole board with copper (except for the spaces between islands). There are a number of reasons for this including:

1. It is good to match the GND plane cover fully with PWR plane cover.
2. There are potential thermal expansion issues where boards with unbalanced PWR/GND plane copper coverage can lead to board becoming warped.

The one main exception I can think above for the above is that on designs where there are high current switcher supplies the 'switching node' between the switch FET, inductor and diode (or 2nd FET for a synchronous switcher) want to have a component side island to interconnect the node. This node should have a copper cutout in the PWR/GND layers so the it is not able couple noise into the power and ground.