this is my first time on stackexchange and I have a question. I have a project and I have to write a vhdl code but when i simulate i get a unknown output. I don't know why but i dont get a error at compiling. It is just a simple fsm that take a average of 8 bit vector. can someone tell me what is wrong? thx
library IEEE;
use IEEE.std_logic_1164.ALL;
entity delay is
port(mem_in :in std_logic_vector(7 downto 0);
flag_in_mem :in std_logic;
reset :in std_logic;
clk :in std_logic;
enable :in std_logic;
flag_out_main:out std_logic;
data_out :out std_logic_vector(7 downto 0));
end delay;
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
architecture behaviour of delay is
type delay_state is (main, regi, calc);
signal state, new_state: delay_state;
signal reg, new_reg,buff, new_buff : std_logic_vector(7 downto 0);
signal test : std_logic;
begin
lbl1 : process(clk,reset)
begin
if(reset='1') then
state <= main;
reg <=(others =>'0');
data_out<=(others =>'0');
flag_out_main<='0';
elsif (clk'event and clk='1') then
state <= new_state;
reg <= new_reg;
buff <= new_buff;
end if;
end process;
lbl2 : process(mem_in, enable, state, flag_in_mem, reg,buff)
begin
new_state <= state;
new_reg<=reg;
case state is
when main =>
flag_out_main<='0';
if (flag_in_mem='1' and enable='1') then
new_state<=calc;
end if;
when calc =>
new_buff <= std_logic_vector((unsigned(mem_in) + unsigned(reg))/2);
flag_out_main<='1';
new_state<=regi;
when regi =>
if(enable='0') then
new_reg<=buff;
new_state<=main;
end if;
end case;
end process;
data_out<=reg;
end behaviour;
