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I am new to VHDL and tried to implement a simple example from a book, what represents a 2bit register and the testbench.

Compiling the files works well, and signals the stimulate the register (reset, clock and data) are correctly transmitted from the testbench to the register.

But the assignment of internal signals to any value remains without any action, thus there is also no output.

I tried to simulate it with ModelSimPE Student Version and Xilinx Viacom Webpack edition 2014.3 .

In both IDEs I included the files, and they compile without any errors. q0_s, q0_ns, q1_s, q1_ns will not change their values, and thus there is no output.

Can anyone tell me, what is wrong with my code?

The 2bit register

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY reg2 IS
    PORT (
        clk : IN  std_logic;
        d0  : IN  std_logic;
        d1  : IN  std_logic;
        load: IN  std_logic;
        res : IN  std_logic;
        q0  : OUT std_logic;
        q1  : OUT std_logic
    );
END reg2;

ARCHITECTURE beh OF reg2 IS
    SIGNAL q0_s, q0_ns, q1_s, q1_ns : std_logic;
BEGIN
    reg : PROCESS (clk, res)
    BEGIN
        IF res = '1' THEN
            q0_s <= '0';
            q1_s <= '0';
        ELSIF clk'event AND clk = '1' THEN
            q0_s <= q0_ns;
            q1_s <= q1_ns;
        END IF;
    END PROCESS reg;

    q0 <= q0_s AFTER 2 ns;
    q1 <= q1_s AFTER 2 ns;

    mux : PROCESS (load, q0_s, q1_s, d0, d1)
        BEGIN
            IF load = '1' THEN
                q0_s <= d0 AFTER 3 ns;
                q1_s <= d1 AFTER 3 ns;
            ELSE
                q0_ns <= q0_s AFTER 4 ns;
                q1_ns <= q1_s AFTER 4 ns;
            END IF;
    END PROCESS mux;


END beh;

Testbench

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY test_bench IS
END test_bench;

ARCHITECTURE reg2_test OF test_bench IS

    COMPONENT reg2
        PORT (
            clk : IN  std_logic;
            d0  : IN  std_logic;
            d1  : IN  std_logic;
            load: IN  std_logic;
            res : IN  std_logic;
            q0  : OUT std_logic;
            q1  : OUT std_logic
        );
    END COMPONENT;

    -- stimulus signale
    SIGNAL s_clk  : std_logic := '0';
    SIGNAL s_d0   : std_logic := '0';
    SIGNAL s_d1   : std_logic := '0';
    SIGNAL s_load : std_logic := '0';
    SIGNAL s_res  : std_logic := '0';

    -- response signale
    SIGNAL q0_r : std_logic;
    SIGNAL q1_r : std_logic;

    -- Verschaltung des DUV mit den Stimulus/Response signalen
    BEGIN

    u1 : reg2
        PORT MAP ( clk => s_clk, d0 => s_d0, d1 => s_d1, load => s_load,
                res => s_res, q0 => q0_r , q1 => q1_r);
    -- Taktgenerator ( 100MHz )
    s_clk <= NOT s_clk AFTER 5 ns;

    -- Stimuli
    stim : PROCESS
        BEGIN
            s_res <= '1', '0' AFTER 20 ns;
            s_d0 <= '1' AFTER 20 ns;
            s_load <= '1' AFTER 40 ns;
            WAIT;
    END PROCESS stim;

    -- Abbruch der Simulation
    stop_sim: PROCESS
    BEGIN
        WAIT FOR 100 ns;
        ASSERT false  REPORT "simulation stopped" SEVERITY failure;
    END PROCESS stop_sim;
 END reg2_test;
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You have multiple drivers for q0_s and q1_s:

architecture beh of reg2 is
    signal q0_s, q0_ns, q1_s, q1_ns : std_logic;
begin
    reg : process (clk, res)
    begin
        if res = '1' then
            q0_s <= '0';
            q1_s <= '0';
        elsif clk'event and clk = '1' then
            q0_s <= q0_ns;
            q1_s <= q1_ns;
        end if;
    end process reg;

    q0 <= q0_s after 2 ns;
    q1 <= q1_s after 2 ns;

    mux : process (load, q0_s, q1_s, d0, d1)
        begin
            if load = '1' then
                q0_s <= d0 after 3 ns;
                q1_s <= d1 after 3 ns;
            else
                q0_ns <= q0_s after 4 ns;
                q1_ns <= q1_s after 4 ns;
            end if;
    end process mux;


end beh;

Each process has it's own drivers for any signals assigned within that process.

The value of the signals is the resolved value of the two drivers, std_logic is a resolved type. It uses the resolution function and resolution_table found in the body of the std_logic_1164 package to perform that resolution.

These two assignments to q0_s and q1_s should be to q0_ns and q1_ns like found in the else:

mux : process (load, q0_s, q1_s, d0, d1)
    begin
        if load = '1' then
            q0_ns <= d0 after 3 ns;  -- was to q0_s
            q1_ns <= d1 after 3 ns;  -- was to q1_s

This gives a better result:

test_bench_reg2.png

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  • \$\begingroup\$ That worked, thanks a lot. I posted this questions, before I've read the chapter about the IEEE std_logic type. Now that I know what the Problem the was, and what the 'U' value means it all makes sense. \$\endgroup\$ – lamchob Oct 10 '14 at 15:36

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