Is there way to calculate slew rate of following circuit?


simulate this circuit – Schematic created using CircuitLab

Datasheet for Transistor

Datasheet for Diode

I chose the PMOS and Diode arbitrarily from what I could choose from Circuit Lab.

If VTRIG goes from 5V to 0V, how can I calculate the slew rate (V/us)?

  • \$\begingroup\$ Uhhh datasheet? \$\endgroup\$ – Bradman175 Dec 26 '16 at 1:43
  • \$\begingroup\$ @Bradman175 I've added link to datasheet \$\endgroup\$ – Steve Dec 26 '16 at 2:19
  • \$\begingroup\$ Now go into dynamic under specifications and look at the delay and rise fall times? \$\endgroup\$ – Bradman175 Dec 26 '16 at 2:52
  • \$\begingroup\$ poor choice of FET for -5V Vgs \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 26 '16 at 3:27
  • A rough approximate is to use the RdsOn for -5V.
  • It is guaranteed to be 0.3Ω but that is for -10V @25'C with 7.2A Pulse, width = 300 μs; duty cycle = 2 %.
  • your situation is different and vague;
    • Initial conditions :
    • Vcap (unknown )
    • Cap part number (unknown ) and
    • trace inductance (unknown )
    • cap ESR or Dissipation Factor (unknown )
    • Diode ESR 1N4148 0.1W ~ 10ohm ( assumed to be larger than 1nF
    • Cap ESR which is expected to have ESR*C value=T < 0.1us for ceramic
    • The RdsOn starts at a high value due to Vdes =5V and Vgs=-5V and not being a "logic level" gate controlled FET requires a certain amount of calculations from the datasheet below enter image description here

With the slew rate being dV/dt=Ic/C for the cap and Ic = (V+-Vcap)/(RdsOn+ESR(diode)) it becomes highly nonlinear.

But with initial conditions of ESR diode=10, and ESR or RdsOn of FET=10Ω then dropping to 0.34 Ω as Vds drops below 3V.

  • Ic=C dV/dt=1e-9 * (5V)/(10Ω+10Ω) and C= 1e-9F for Vds=3~5V

slew rate dV/dt= Ic/C= 5V/20Ω*1e9= = 0.25V/ns

Low confidence in results due to inadequate info.


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