- A rough approximate is to use the RdsOn for -5V.
- It is guaranteed to be 0.3Ω but that is for -10V @25'C with 7.2A Pulse, width = 300 μs; duty cycle = 2 %.
- your situation is different and vague;
- Initial conditions :
- Vcap (unknown )
- Cap part number (unknown ) and
- trace inductance (unknown )
- cap ESR or Dissipation Factor (unknown )
- Diode ESR 1N4148 0.1W ~ 10ohm ( assumed to be larger than 1nF
- Cap ESR which is expected to have ESR*C value=T < 0.1us for ceramic
- The RdsOn starts at a high value due to Vdes =5V and Vgs=-5V and not being a "logic level" gate controlled FET requires a certain amount of calculations from the datasheet below
With the slew rate being dV/dt=Ic/C for the cap and Ic = (V+-Vcap)/(RdsOn+ESR(diode)) it becomes highly nonlinear.
But with initial conditions of ESR diode=10, and ESR or RdsOn of FET=10Ω then dropping to 0.34 Ω as Vds drops below 3V.
- Ic=C dV/dt=1e-9 * (5V)/(10Ω+10Ω) and C= 1e-9F for Vds=3~5V
slew rate dV/dt= Ic/C= 5V/20Ω*1e9= = 0.25V/ns
Low confidence in results due to inadequate info.