I am working on a design which involves an FPGA having an external clock, the clock source is supposed to be programmable clock synthesiser, however this needs to be programmed at power on by the FPGA to output the correct clock frequency. I don't have great experience in this domain, but I am kind of sure that the FPGA will not operate correctly without an appropriate clock.
My solution to this is to use a 125MHz crystal, which is connected to a programmable clock multiplexer. At power on the FPGA will receive the clock from the oscillator, after this it will program the clock synthesiser and switch the clock source on the clock multiplexer. The purpose of this is to have a precise phase synchronised system. My BIG issue with this is that I don't know if it is safe to disrupt the clock being delivered to the FPGA and if it will remain operational during this switchover phase. Hopefully someone may have a better idea of how FPGA's behave with regards to the clock.
The FPGA in question is a Xilinx ZC7Z010 Cortex A9. I am welcome to other ideas, but the FPGA most certainly needs to be clocked by an external oscillator.
Many thanks for reading this.