I am really confused with all of the ground bounce, decoupling, bypassing, filtering, resonance and ESR&ESL stuff.

What I currently understand is:

  1. Ground bounce occurs when the (capacitive part of the) load trying to source (and at the same time IC trying to sink) the current which has a high enough \$\dfrac{di}{dt}\$. Lead inductances of the package do not matter much, however other inductances of the traces which are bigger compared to the IC leads matter. That's why capacitor(s) are put as close as to the IC power pins to provide a spontaneous power supply that is close enough and have small path inductance enough to prevent ground bounce.

  2. Decoupling is the job of the capacitor mentioned above. Also, it will bypass the noisy sub-circuit from the quiet sub-circuits by preventing high currents that have \$\dfrac{di}{dt}\$ to distribute to the other parts of the board.

  3. Also, a decoupling capacitor will filter unwanted high or low frequency noise from the power supply by giving the noise a least inductance path to the ground.

  4. Resonance frequency plot of the capacitor will show us how effective it is at a frequency.

My questions are:

  1. If one uses 1nF, 100nF (both polyester film box type) and 10uF (electrolytic) through hole capacitors near the the power input of the PCB, like in the below layout, (s)he obviously won't be able to decouple the ICs that are far away, however will (s)he be able to suppress the noise coming from the power supply of the system? Is a 1nF, 10nF or 100nF capacitor effective for this job?
  2. May be the same question as above. Is putting a 1nF, a 100nF and a 10uF capacitor on the power bus of a breadboard effective?
  3. Can decoupling capacitors cause oscillations?

Below is a PCB I tried to lay out. It is an audio amp that is used in the buses so the +24V power supply input in the "input & output connector" is noisy. In the schematic I was given, there were lots of capacitors and an inductor (in both SMD and through-hole package, only one is populated). L1, C7, C8, C10, C9 are the components I am talking about. Are these capacitors effective by the means of first question? Also, do C10, L1 and C7 form an effective Pi filter?

Edit: Sorry, I had to remove the PCB and the schematic due to company policies. Oops!


1 Answer 1


There is a lot here that is difficult to cover. I'll do my best, but be aware that I am leaving things out on purpose. I simply can't cover every issue in the space and time that I have.

You have two main problems: 1. You are basing your electrical design off of old ideas and old rules-of-thumb. 2. You are over thinking things a LOT, especially given the performance of (or lack thereof) your audio amp chip. Let's go over your numbered points:

  1. For most things, ground bounce is a non-issue and can be lumped into the bigger category of power and ground noise. This is a bigger issue when you have very fast switching signals and/or are switching a lot of power. Your amp is not switching a lot of power (only 14 watts), and is not switching quickly (you're not even switching digitally). What you need to be concerned with is making sure that your power and ground distribution has the lowest possible impedance/resistance between all of the parts on your board. Sure, place the caps near where they will be used, but don't stress about it.
  2. Assuming that you have low impedance/resistance connections to power/gnd on your PCB, the primary purpose of decoupling on your board is going to be bulk capacitance where power comes into your board. You want to minimize the effects of the power cable impedance, and bulk caps where that cable connects is the best way to do that. Of course you should put more caps at the power pins of each chip, but at audio frequencies this just isn't that important.
  3. Yes, decoupling will filter noise from the power supply. Your bulk capacitors from #2, above, will do a lot of that. The components on your PCB itself won't be generating a lot of noise (assuming that you got #1 correct).
  4. Remember that audio frequencies are only up to 20 KHz, and much of what you've read about decoupling caps and ground bounce are typically saved for digital switching well above 1 MHz. You're correct, but it doesn't matter much if at all in your case. Almost every cap that you will use for decoupling will be effective at less than 20 KHz.

Another thing to keep in mind is that your amp chip has a typical distortion of 0.1%. This is a lot higher than any improvement you are considering. For example, doing some sort of ground-bounce analysis of your PCB might improve your distortion figure by 0.0001%. But that means that your total distortion might go from 0.1000% to 0.1001%. It just doesn't matter!

Now, let's go to your questions:

  1. For bulk decoupling caps at the power input I would go with the largest reasonable electrolytic caps that you can fit on the PCB. The exact size depends on what the power source is and how long the cable is. If you were using a wall wart over a 6 foot cable then I would want at least a 680 uF cap, or better yet three 220 uF caps. Going up to 1000 uF would not be overkill. But if your power supply is a lot closer, and the cable is shorter, then using something smaller is OK. I would not go below a single 470 uF cap. A single 0.1 to 1.0 uF ceramic cap would also be good, but not required. At each TDA2030 chip use both a 100 uF cap and a 0.1 to 1.0 uF cap per power pin.
  2. Power on a breadboard is rarely ideal. The lead inductance of the caps and the breadboard itself often much higher than what you really want. Putting caps on the power of a breadboard is helpful, but you will never make breadboard power as good as power on a well-done PCB.
  3. Yes, decoupling caps can cause oscillations, but this is rarely a problem. The best way to prevent this is to reduce the impedance/inductance of your power and ground signals on your PCB. This brings us to your PCB layout...

You're PCB layout is bad. The main problem is that you are using a "star-ground". Star-grounds are often the wrong thing to use. A PCB like this, where there isn't a lot of noise being generated and everything is fairly close together, a star ground doesn't provide any benefit and often harms things.

Ideally what you want is a 4-layer PCB where one inner layer is a solid ground plane, and the other inner layer is a solid power plane. This provides the absolute lowest power and ground impedance across the entire PCB. (In a moment I'll tell you what to do on a 2 layer PCB.)

What you have are a bunch of individual power/gnd traces that are relatively narrow and will have an impedance that is much higher than a solid plane. Also, the distance between different components is large. For example, the GND path from C3 to U1.3 is three times longer than it should be. Not only will this increase noise, but it increases the loop area. A larger loop area is going to increase your suseptability to external RF noise.

You have similar issues on the power traces. They are relatively narrow and long. This is going to increase the trace impedance and reduce the effectiveness of your decoupling caps.

The correct way to do the PCB layout in 2 layers is to fill the PCB with copper planes. The blue layer would have the GND plane, while the red layer the V+ plane. These planes will be "chopped up" with signal traces, of course, but you will have to carefully route those signals to minimize the negative effects of chopping up the planes.

  • \$\begingroup\$ Thanks for the great answer again, David! Yes, I am really confused with these stuff. The one who designed the circuit is my dad, he is a fellow electronics engineer with 30 years of experience, but as you guessed, he really is a rule of thumb kind of engineer and his rules of thumb are old. So, what I understand is C7, C8 and C9 are not needed. C4 and C16 are better raised to 1uF ceramic, and star-grounding is bad when it is done with no thought of return currents. \$\endgroup\$ Commented Apr 6, 2012 at 15:28
  • \$\begingroup\$ I have one more question though; if I create a copper fill of GND in the blue layer, should I include the output return in this copper fill? Since this return path will carry high current, will it create voltage differences in the ground fill, or will it create any other problems like coupling back to the input? \$\endgroup\$ Commented Apr 6, 2012 at 15:31
  • 1
    \$\begingroup\$ @abdullahkahraman You want C7, but C10 can be removed. C8/C9 is not needed. C4/16 to 1uF. And add 100 uF on the power pins of U1 and U2. The copper plane will have voltage differences, but these will be much smaller with a plane vs. star ground. Also a 14 watt amp won't create enough of a difference to matter. \$\endgroup\$
    – user3624
    Commented Apr 6, 2012 at 15:52
  • \$\begingroup\$ Lots of other questions really pop into my mind if you could help me out? In high frequencies (250 KHz and above?), like you have told me in my SMPS designs before, current tries to return almost right under the signal track, trying to minimize the loop area. What does DC to 20 KHz do in a ground plane? Will it spread everywhere since it will try to follow the least resistance path (I've read that somewhere)? That way (I am guessing only), the return currents in the ground plane will mess up! Please tell me I am wrong! \$\endgroup\$ Commented Apr 6, 2012 at 16:07
  • 1
    \$\begingroup\$ @abdullahkahraman At DC the return currents follow a direct path. At 20 KHz they are closer to under the signal trace. You should design your PCB assuming the return currents follow the trace since distortion is harder to control at higher frequencies. But this effect is going to be minimal on this PCB anyway, and still much smaller than the 0.1% distortion of the amp. \$\endgroup\$
    – user3624
    Commented Apr 6, 2012 at 16:17

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