Computing a mathematical expression using half and full adders

Question

I am new to logical desing and I am not sure how to start the exercise.

The problem:

Assume that we have 2 assinged numbers of 2 bits (A = a1 a0 and B = b1 b0). Desing a combinational logical circuit that computes the S = 4A + 3B and uses half and full adders, only.

What I am thinking is to use 2 full adders to compute the "4 * A", another 2 to compute the "3 * B" and another one to compute the S = 4A + 3B. This mean that I will need 5 full adders in total.

Is this the best and most efficient solution? I guess no but I can't think something better.

Is this diagram right?

Answer 1

First, realize that multiplying a binary number by a power of 2 can be done by simply shifting the number, and no adders are required. Also, 3B can be written as 2B + B.

So your required calculation becomes

     a1 a0  0  0    (4 A)
           b1 b0    (B)
+       b1 b0  0    (2 B)
----------------
  s4 s3 s2 s1 s0

If you notice that it doesn't require an adder to add 0 to something, you can simplify this to

     a1 a0 b1 b0    (4 A + B)
+       b1 b0  0    (2 B)
----------------
  s4 s3 s2 s1 s0

I believe this can be implemented with 2 half-adders and one full-adder, but I'll leave it to you to work out how and to draw it as a schematic diagram.