Literature covers very well the decoupling of many pin types on a microcontroller, such as from muRata and E2V. The currents in are decoupled from the ground plane. PLL's are also grounded, however I have not read anything about decoupling them. Do PLL pins need decoupling in the same way as power pins?
For instance, Atmel detail the decoupling of VDD and VDDGND pins and describe the clock circuits for one of their MCU's. They do not detail any decoupling of their GNDPLL at all.
Any PLL you choose (part of an MCU or not) should have the information in the relevant data sheet. If it doesn't then you might need to dig a little deeper in the case of generic parts such as a 4046 but, at the end of the day, there will be data sheet information that gives decent guidelines and you should follow these guidelines.
If you have come across a PLL that doesn't give good information then you have to decide if it is worth the risk.
For instance, Atmel detail the decoupling of VDD and VDDGND pins and describe the clock circuits for one of their MCU's. They do not detail any decoupling of their GNDPLL at all.
It's highly likely that there is an assumption that those pins connect directly to the ground plane and need no special treatment. It might also be the case that those particular ground pins need to be treated like a small copper island and that the PLL power pins need decoupling directly to that island of copper. The copper island would, quite possibly, have a single point connection to the main ground plane.
Assuming you mean PLL power pins by saying "PLL pins", you must decouple them essentially the same way as you decouple other digital ICs.
There are three main aspects of decoupling:
1. Providing a low impedance current return path for circuitry to ensure stable operation.
2. Controlling interference. When a current return path forms, it might coincide with another current path and Common impedance coupling forms. If your analog path coincides with digital path, you get noise.
So yes, PLL needs similar treatment as other digital ICs.
The Vdd,Vss is used for both the logic mixer and VCO will affect phase noise, so decoupling is as important as your phase noise spec.
Following all the LC decoupling advice and even integer dividers with good layout practices used in their Eval Kit, ought to be sufficient.
