The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count value is compared to a 5-bit input data value, and if the count value is greater-or-equal to the data value, then a flag is set. This flag is used as an input to a small FSM. The FSM diagram and datapath circuit is shown in the attached figure
The max clock frequency design goal is 100 MHz, but via the TimeQuest timing analyzer tool in Altera Quartus, I get Fmax = 92 MHz.
Is the design goal to strict or should I normally be able to achieve this clocking frequency ?
Note that the clock frequency is based on setup timing considerations. There are no PLLs or internally generated clocks.
Also note that the failing paths (there are two) are between the count-value bits, q_1/q_0 and a bit for the state encoding: state2...