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The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count value is compared to a 5-bit input data value, and if the count value is greater-or-equal to the data value, then a flag is set. This flag is used as an input to a small FSM. The FSM diagram and datapath circuit is shown in the attached figure

FSM and datapath

The max clock frequency design goal is 100 MHz, but via the TimeQuest timing analyzer tool in Altera Quartus, I get Fmax = 92 MHz.

Is the design goal to strict or should I normally be able to achieve this clocking frequency ?

Note that the clock frequency is based on setup timing considerations. There are no PLLs or internally generated clocks.

Also note that the failing paths (there are two) are between the count-value bits, q_1/q_0 and a bit for the state encoding: state2...

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  • \$\begingroup\$ BTW, the state transitions are all synchronous to the clock, exept that associated with the global reset, resetMain, which asynchronously can reset the FSM to the idle-state. Also, the FMS is a Moore-type \$\endgroup\$
    – drC1Ron
    Commented Nov 7, 2017 at 23:54
  • \$\begingroup\$ There should be a report on the critical (slowest) path. Have you check the max frequency on the individual modules? Does can LPMcounter run at 100 MHz on its own? \$\endgroup\$
    – Greg
    Commented Nov 8, 2017 at 16:14
  • \$\begingroup\$ @Greg Yes, the LPMcounter - as well as combined with the LPMcompare, can run on more than 100MHz... \$\endgroup\$
    – drC1Ron
    Commented Nov 8, 2017 at 21:20

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