I was going through some reference design from Altera's Wiki and ran into the following piece of code:
always @* begin in_ready <= out_ready || ~out_valid; end
My understanding is that having a flip-flop like that helps get more deterministic timing, synthesis tool can refuse to synthesize if
out_ready || ~out_valid combinatorial delay exceeds the limit and timing requirements are not met etc. Other than that, that should be en equivalent of the following combinatorial description:
assign in_ready = (out_ready || ~out_valid);
What made me think about it is the larger piece of code that I am readying. Sometimes combinatorial logic is used to drive the "ready" output of some modules, but sometimes this style. I cannot really spot a functional difference and see an obvious explanation.
I've read somewhere that combinatorial logic is not welcome in FPGAs because of timing issues and synchronized design is always preferred, and this project specifically targets FPGAs. But the mixing is what confuses me. So two questions popped out in my head:
- When and why one solution should be preferred over another?
- Is there any difference in behavior (or analysis of the design) when the output of the module is "reg" versus when it is a "wire"?
Any help is appreciated. Thank you.