I have the little doubt related to initializing condition in Verilog. Like in given statement:
module rf(out1,ack,en,a,f,c,d,e,clka); input [7:0] a,f,c,d,e; input clka, en; output reg [7:0] out1; output reg ack; reg[7:0] b[1:5]; reg [1:0] first=0; reg [2:0] k; initial begin for (k = 1; k <6; k = k + 1) begin b[k] = 0; end end always @(negedge clka) begin if (en==1) begin if (first==0) begin first<=1; end if (first==1) begin first<=2; b<=a; b<=f; b<=c; b<=d; b<=e; end end end endmodule
I initialized reg first =0 ; Is it right ? As it is giving right result after simulation but is there any problem when we will synthesize it? I used the first condition because I wanted to execute statements written within (first == 1 ) execute after one clock pulse.
Is it the right way? If not then what should I do if I want to execute few statements after one or two clock pulse ?
Hope I explained my confusion clearly.
module median_five_sh(out1,ack,reset,a,f,c,d,e,clka); input [7:0] a,f,c,d,e; input clka,reset; output reg [7:0] out1; output reg ack; reg en0,en1,en2,en3,en4,en5,en6,en7,en8,en9; reg[7:0] b[1:5],tmp; reg first; reg [3:0] i1,i2,n1,k; initial begin for (k = 1; k <6; k = k + 1) begin b[k] = 0; end end always @( posedge reset) begin en0<=0;en1<=0;en2<=0;en3<=0;en4<=0;en5<=0;en6<=0;en7<=0;en8<=0;en9<=0; first<=0; i1<=0;i2<=0;n1<=0;k<=0; tmp=0; end always @(negedge clka) begin if (reset==1) begin statement; en0<=1; en1<=1; . . end end endmodule
The above code is simulating and giving correct output but it is giving the error after synthesis.
**Error: Signal en0 in unit .... is connected to following multiple drivers:
* I wanted to execute statements written in always @( posedge reset) only once while initially. Basically its initialization of variables used in later statment.