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I am trying to test a very simple deskew circuit on a virtex-2pro FPGA (xc2vp30-fg676-5). I use xilinx ISE and the deskew IP (two DCMs with a DDR flop) provided by core generator. I also try to observe the related signals on GPIO pins. But I have got the following translate error in my design. The details of the error and the design is pasted below. Please give me some hints.

Resolving constraint associations...
Checking Constraint Associations...
ERROR:ConstraintSystem:59 - Constraint <INST "rex_clk"  LOC="N3" |>
   [xc2vp30.ucf(14)]: INST "rex_clk" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD="LVCMOS33" ;>
   [xc2vp30.ucf(14)]: INST "rex_clk" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

Done...
Checking Partitions ...

Checking expanded design ...
ERROR:NgdBuild:809 - output pad net 'clk_o' has an illegal load:
     pin C on block cnt_0 with type FDC

Verilog module

module xc2vp30(
    //probing
    output rex_clk,
    output rex_rst,
    output rex_cnt_i,
    output rex_cnt_o,

    input rst,
    input clk,
    output clk_o,
    output rst_o,

    input cnt_i,
    output cnt_o
);

wire clk_ddr;
reg cnt;

assign rex_clk = clk_ddr;
assign rex_rst = rst;
assign rex_cnt_o = cnt;
assign rex_cnt_i = cnt_i;

assign clk_o = clk_ddr;
assign rst_o = rst;
assign cnt_o = cnt;


always @(posedge clk_ddr or posedge rst) begin
    if(rst)
        cnt <= 1'b0;
    else
        cnt <= cnt + 1'b1;
end

////////////////////Deskew/////////////////////

deskew deskew_0(
    .U1_CE_IN(1'b0),
        .U1_CLKFB_IN(clk_ddr),
        .U1_CLKIN_IN(clk),
        .U1_CLR_IN(rst),    //high reset
        .U1_PRE_IN(1'b0),
        .U1_RST_IN(rst),    //high reset
        .U2_RST_IN(rst),
        .DDR_CLK0_OUT(clk_ddr),
        .U1_CLKIN_IBUFG_OUT(),
        .U1_CLK0_OUT(),
        .U1_CLK180_OUT(),
        .U1_LOCKED_OUT(),
        .U2_CLK0_OUT(),
        .U2_LOCKED_OUT()
);
endmodule

UCF file

NET "clk" PERIOD = 40 ns HIGH 50%;
NET "clk" TNM_NET = clk;
#================================================ Pin assignment
#------------------------------------------------ Clock, reset, LED, and SW.
INST "clk"          LOC="B13" | IOSTANDARD="LVCMOS33";           # Clock input (X2)
INST "rst"             LOC="E21" | IOSTANDARD="LVCMOS33";           # Reset input

INST "clk_o"       LOC="AE1" | IOSTANDARD="LVCMOS33";              # Clock output
INST "rst_o"          LOC="Y26" | IOSTANDARD="LVCMOS33";               # Reset output
INST "cnt_o"          LOC="U2" | IOSTANDARD="LVCMOS33" | DRIVE=6;  # data output
INST "cnt_i"          LOC="V5" | IOSTANDARD="LVCMOS33" | DRIVE=6;  # data input

INST "rex_clk"     LOC="N3" | IOSTANDARD="LVCMOS33" ;           #  observe clk output
INST "rex_rst"     LOC="M4" | IOSTANDARD="LVCMOS33"| DRIVE=6; # observe Reset output

INST "rex_cnt_i"     LOC="L3" | IOSTANDARD="LVCMOS33"| DRIVE=6; # observe
INST "rex_cnt_o"     LOC="K3" | IOSTANDARD="LVCMOS33"| DRIVE=6; # observe
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  • \$\begingroup\$ Are you using straight Xilinx tools, or is this e.g. Altium which is then being passed along to Xilinx? Some third-party EDAs can do some tricks which can screw up naming certain signals \$\endgroup\$ – ajs410 Jun 21 '12 at 20:03
  • \$\begingroup\$ @ajs410, I am using ISE and core generator. Both of them are from xilinx. \$\endgroup\$ – drdot Jun 21 '12 at 20:32
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That Verilog module is top-level, right? Make sure, because the toolchain will try to map the UCF onto the top level module. If you're using a third-party toolchain that "sits above" the Xilinx toolchain, you will want to investigate what top-level file the third-party toolchain is creating.

I looked in my UCF files and I don't see INST at all. I use NET everywhere (with the exception of one TIMESPEC on the main clock)


Another thing I noticed...

always @(posedge clk_ddr or posedge rst) begin
    if(rst)
        cnt <= 1'b0;

You are using posedge on two different signals. Pin C on FDC probably means the "clear" pin of a D Flip Flop (hence, FDC). You probably actually want an FDCE (D Flip Flop with async Clear and clock-Enable), or an FDE (D Flip Flop with clock-Enable). The synther is probably confused because flip flops only have one edge-sensitive input and you're asking it for a flip flop with two edge sensitive inputs.

Did you want an async clear, or a sync clear? If async, get rid of the "posedge" in front of rst. If sync, get rid of the entire "posedge rst". Async clear (FDCE) is trouble unless you know what you're doing; go for the sync clear (FDE).

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  • \$\begingroup\$ Thank you for the comment of the coding style! Yet I dont understand why the synthesizer would be confused if i code it like this? (regardless of the coding style). Since I wrote seveal designs using async high clear on FPGA. \$\endgroup\$ – drdot Jun 27 '12 at 2:36

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