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I'm trying to understand if I can use a V1401 ADAT transmitter with the PCM4222 ADC.

datasheets:

Coolaudio V1401

TI PCM4222

They will be communicating by their PCM audio serial port interfaces, using Left-justified mode. The ADC will be set as master, it will get a master clock from an external oscillator. Doing so, it will generate LRCK and BCK. V1401 only needs word clock, since it generates its own internal BCK using a PLL (f = 64xWDCLK).

So can I connect V1401 WDCLK input to PCM4222 LRCK output?

my doubts are:

1) for the sample rates that I need, PCM4222 will produce 128*Fs and 256*Fs for the BCK, and V1401 uses 64*Fs as internal BCK. Does it matter? Or I shouldn't care, since they don't share BCK? if so, PCM4222's LRCK would still be at the correct rate for V1401?

2) how should I set WDCLKNEG of V1401 (WDCLK phase)?

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1 Answer 1

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The ADAT part is really odd ... I presume it's a relic of the 1990's Alesis ADAT 8 channel tape system. Anyway it appears (from the datasheet) to use a UART style interface relying on the relatively low jitter of a crystal generated 48 kHz LRCK.

So it generates a 64*Fs clock and keeps it internal, relying on incoming data to appear on the pins at exactly the right time (stable around the middle of each 64*Fs period. (Page 3, figure 1 and text).

Which is what you need from the ADC.

Now the only way I can see to get that directly from the ADC is at Fs = 48 kHz, in left justified mode, with BCK freq = 64* Fs.

Which the ADC does not support in master mode (p.21)

For the I 2 S and Left-Justified data formats, the BCK clock output rate is fixed in Master mode, with the Normal mode being 128fS

However the BCK pin can be an input, and BCK = 64*Fs is then supported:

In Slave Mode, a BCK clock input rate of 64f S or 128f S is recommended for Normal mode, while 64f S is recommended for Double and Quad Rate modes.

So I think you have to use the ADC in Slave mode. That means you need to supply it with:

  • MCKI : 256*Fs = 12.288 MHz
  • BCK : 64*Fs = 3.072 MHz, with the correct hase relationship to LRCK
  • LRCK : Fs = 48 kHz.

Not difficult (ignoring any other consequences of operating it in Slave mode) Now the real Master is your clock generator, which supplies LRCK to both ADC and ADAT.

Question 2 : how do I set WDCLKNEG ?

By referring to the detailed description on each datasheet, and noting carefully which channel is L and which is R on the ADC.

Then if the violins come blasting into your right ear, inverting it.


Leaving the big question : why choose the ADAT in the first place?

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  • \$\begingroup\$ thank you! I don't understand something.. if the ADAT chip generates BCLK from Fs*64, that means it doesn't need BCLK from outside, and it only needs Fs. So, using the ADC in master mode, I have LRCK as output = Fs. Then I can supply this to the ADAT chip. Am I missing something? Also, I choosed ADAT because the audio interface that I'm trying to expand with more inputs has got the ADAT port only \$\endgroup\$ Sep 28, 2019 at 17:42
  • \$\begingroup\$ Yes. If LRCK is an OUTPUT from the ADC, then so is BCK. Which means BCK is 128*FS, the data comes out twice as fast as you want, and the ADAT will only see every second bit of data. \$\endgroup\$
    – user16324
    Sep 28, 2019 at 17:46
  • \$\begingroup\$ The would a simple flip flop be enough to divide by 2 the LRCK clock going to the ADAT chip? \$\endgroup\$ Sep 28, 2019 at 19:01
  • \$\begingroup\$ That would give you a 24 kHz LRCK. \$\endgroup\$
    – user16324
    Sep 28, 2019 at 22:17
  • \$\begingroup\$ I asked Texas Instruments about LRCK rate when the device is master, and it is always equal to Fs. So I think connecting this to word clock input of ADAT chip would work. Or am I missing something? \$\endgroup\$ Oct 2, 2019 at 15:26

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