[![the output of my GPIO is 1.8V which is pulled up to 3.3V using a 4.7K resistance and that gpio is connected to the gate terminal of a P-channel mosfet, when i measure voltage across the gate terminal it results in 1.8V and i got 1.8325V by nodal analysis at gate terminal but i'm not getting why so, can anyone provide me what things should i learn to solve these kind of problems]]
closed as unclear what you're asking by TonyM, Finbarr, Chris Stratton, DKNguyen, Elliot Alderson Oct 19 at 12:32
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The output is very likely a push pull stage which has a (relatively) low output resistance.
What you effectively have is this (assuming you are using a CMOS device)
The output when high will have M2 on and M1 off.
The output of this stage when high will have a typical resistance to 1.8V of perhaps a few tens (sometimes higher) of ohms; the voltage divider formed of M2 and the pullup resistor will maintain the output voltage at close to the GPIO drive voltage of 1.8V
You could use an open drain output but ensure it is safe to use with a 3.3V pullup (that will be in the datasheet).
The effective circuit in the high output state is this:
From the voltage divider principle, the voltage at Vout will be 1.83125V (assuming the on resistance of M2 is 100 ohms).
You should not normally pull a push pull / totem pole output beyond its supply voltages whether that be positive or negative.