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I'm just wondering how to access more than 32Kb on a TERASIC DE0 nano. It is based on an Altera Cyclone IV FPGA. https://www.ti.com/lit/ug/tidu737/tidu737.pdf

It has 32Mb DRAM but there are

  • 12 address lines
  • 2 bank select lines
  • 16 data lines

This gives a total of 32Kb. There is a program that is provided called NIOS II which seems to be able to access the memory but there aren't any details about how it works.

So the question is how is the rest of the memory accessed?

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    \$\begingroup\$ You have a lot to learn if you don't know that the address bus on DRAM is multiplexed. 12 address lines can be used to access up to 2^24 words of storage -- that's 32 MB per bank if the words are 16 bits wide. In order to access it, you'll need to implement an SDRAM controller in your FPGA. Altera has lots of documentation about that. \$\endgroup\$
    – Dave Tweed
    Commented Nov 24, 2019 at 22:52
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    \$\begingroup\$ NIOS II isn't a program, it's a logic design. Read up difference between FPGA/CPLD/ASIC (implements a logic circuit) and microprocessors (runs a program), very important to understand the clear distinction. Plenty out there on this. \$\endgroup\$
    – TonyM
    Commented Nov 24, 2019 at 23:00
  • \$\begingroup\$ Thanks for that - I'll have a look at the Altera docs. \$\endgroup\$
    – cup
    Commented Nov 24, 2019 at 23:04
  • \$\begingroup\$ You should also look at the latest version of the DE0 user manual on the Terasic webiste. \$\endgroup\$
    – Caleb Reister
    Commented Nov 25, 2019 at 4:58

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The address bus is used for either column or row address, depending on the control signals (RAS/CAS and friends). I don't know which SDRAM chip is on your board, but they are pretty much standardized these days, and differ mostly in timing and maybe in burst options.

Here is a brief overview: Understanding DRAM Operation. Having said that, definitely find the datasheet for your SDRAM chip - it's very informative!

E.g., my DE10 Lite board has this chip: iS42/45S16320F-7TL.

Yours probably has 12-wide row address, 10-wide column address, in total giving \$2^{12+10+2}\$ = 16M words, which for 16-wide data means 32MB (not 32Mb).

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  • \$\begingroup\$ The basic problem was that the free version of the software didn't have the mega module for accessing the DRAM controller.enabled.so if I wanted to do anything with it, I'd have to do it from scratch. \$\endgroup\$
    – cup
    Commented Dec 19, 2019 at 5:15
  • \$\begingroup\$ SDRAM is not too complicated, there are a few free controllers floating around you can either use as is, modify, or examine to roll your own. \$\endgroup\$
    – Andris Birkmanis
    Commented Dec 19, 2019 at 6:14
  • \$\begingroup\$ As a start, take s look at this tutorial. \$\endgroup\$
    – Andris Birkmanis
    Commented Dec 19, 2019 at 6:15

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