PLL Layout guidelines

Question

I am designing a custom board using HMC833LP6GE. I am taking schematic reference from the Evaluation module. There will be onboard DS-PIC MCU for controlling the PLL. The reference input can be fed external or through an on board crystal.

I am designing it on 4 layer card with following stackup.

TOP - SIGNAL

LAYER1 - GND

LAYER2 - PWR AND GND

BOTTOM - SIGNAL

I am unable to find the layout guidelines for designing.

I need some critical and important points while designing a PLL.

For example:- Loop filter is the heart of the PLL design. What care should i take with respect its placement? Can I place few components on top and few on bottom layer?

Answer 1

The first thing you need to do is determine your maximum frequency, because if it's over 50MHz then it's considered high speed design and transmission line effects start to become a concern. Transmission lines need to be impedance matched to the source and the load, there are many techniques to do this on a PCB. The HMC833LP6GE has a 100Ω-200Ω so that is the range of impedance that the transmission lines will need to be matched to.

I would keep all high speed traces (50Mhz+) on the top layer with no switching to other layers (vias have nH of inductance that can make it difficult to match). Keep the traces as microstrip lines and as short as possible. You'll also need to know the E_r (relative permeability of the PCB material) and the stackup distance between the top and ground plane below) as this affects the impedance of the micro-strip line. I would also keep all high speed components on the top layer. Try and keep the high speed traces as short as possible.

Answer 2

Using the Hertz/volt tuning_factor of the PLL (you may have to assume a number, such as 100MHz/volt), and any nearby interferers, build an interference model.

Establish your tolerance for deterministic jitter, such as what external Black Bricks will induce into your PLL control loop.

Establish an ERROR BUDGET for phase noise (timing jitter).