Miller Capacitance in MOSFET

Question

The above image is regarding the Miller Capacitance present in the MOSFET.

I am finding it tough to understand the concept of Miller capacitance. I am trying and researching documents and videos to understand it.

I am not able to understand the graph.

Question 1: Assume Vdc (as per the image) is 20V. And VG is applied from 0V to 5V.

From the graph, at the initial part, when VG slowly ramps up, Voltage at VDC also increases? How is it possible? I think I am failing to understand the basics of capacitors and capacitance which is why this query arises. Can someone help me to clarify this doubt and help me understand a little more intuitive on this capacitor action during millers effect?

Question 2: Why does the Plateau occur? Can someone help me with the concept of miller plateau?

Answer 1

Well, the situation is quite complicated and I assumed pure resistive load.

For \$V_{IN} = 0V\$ we have \$V_{C_{DG}} = 12V\$ and \$V_{C_{GS}} = 0V\$

But at the very first moment when \$V_{IN}\$ "jumps" to \$5V\$. The voltage at the gate will immediately start to rise toward \$5V\$. As \$C_{GS}\$ begins to charge.

But this rise in gate voltage will start to influence the \$C_{DG}\$ capacitor also. And because the voltage across the capacitor cannot changes instantly. This will slightly increase the voltage at the drain beyond the \$V_{DD}\$ value. And the \$C_{DG}\$ capacitor begins the discharge phase and the discharging current starts to flow.

As I was trying to show here:

And the MOSFET is OFF because \$V_{GS}\$ is well below the MOSFET threshold voltage.

As \$C_{GS}\$ capacitors continue to charge towards \$V_{IN} = 5V\$ the capacitor voltage will reach the MOSFET threshold voltage. This will open the MOSFET and \$I_D\$ current begins to flow. This causes the voltage at the drain, measured relative to the ground will start to decrease. The \$C_{DG}\$ capacitor will now start the discharge into the MOSFET. But to change the voltage at the drain and across \$C_{DG}\$ capacitor current is needed (\$I = C\cdot \frac{\Delta V}{\Delta t} \$) Capacitor current is proportional to the rate of voltage change across it (proportional to how quickly the voltage across the capacitor is changing). Thus, because the voltage at the drain needs to change from \$V_{DD}\$ to \$0V\$. Thus, the \$C_{DG}\$ capacitor needs current for this to happen. And all this current must be provided by an input signal source. And because of a fact that \$\frac{\Delta V}{\Delta t}\$ across \$C_{DG}\$ is much larger than \$\frac{\Delta V}{\Delta t}\$ across \$C_{GS}\$. Almost all the input source current will flow into the \$C_{DG}\$ capacitor. Thus the $\V_{GS}$ will rice very very slowly (Plateau effect).

After sometime when \$C_{DG}\$ discharges process is completed (\$V_{C_{DG}} = 0V\$ ) and the drain voltage reaches \$0V\$. The \$C_{DG}\$ will start a charging phase in the opposite direction. But now the \$\frac{\Delta V}{\Delta t}\$ is small because the drain voltage is at 0V and only the gate voltage now needs to reach the final value \$V_{IN}\$ value.

And in the real world, this process will look like this:

In yellow the voltage at the gate (\$V_{IN} = 5V\$) and in "light blue" the voltage at the drain \$V_{DD} = 12V\$.

Answer 2

Take an opamp with gain of 100,000.

Install a 100pF capacitor from VIn- to the output.

Ground the Vin+

Now apply 1 microvolt sinusoid at Vin-.

The voltage source will have to charge up that 100pF capacitor. The other end of the capacitor will be changing, by 100,000X more voltage.

Since the required charge on a capacitor is Q = C * V, here we have a huge problem, because the effective input capacitor is

• (1 + 100,000) larger than what we expected.

This ratio (1 + voltage_gain) is the Miller Multiplication of the actual capacitor.