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I am designing a sort of "driver" for a high voltage Charlieplexed LED array, since normal GPIOS can't handle 12V. For that, I need to be able to use tri-state logic, which means LOW, HIGH, and HIGH-Z.

The schematic below shows two arrangements of PMOS and NMOS similar to a push-pull configuration using two of these ICs plus two not yet defined NMOS. The first -U1 and U4- define the behavior that can be represented as push and pull, and the second -U3 and U6- are the output enable. (HIGH means enable and LOW means HIGH-Z)

So far, the simulation is running well, however, In the last question I asked someone made me a heads-up about the ideal behavior of the GPIOs and that I should be careful with the 12V present in the gate of the PMOS. To solve that I included these two NMOS -U5 and U2- keeping the voltage of the GPIOS under safe values.

Is this fix correct? can someone note me if I might be overseeing something, I'm still a noob at this. Also, I'm simulating with NI Multisim 14.2

Note1: I'm aware of the body effect difference that U1 and U4 will have with respect to U3 and U6 since the body/bulk terminal is kept shorted to the source terminal and not Vcc/Vss. However, I think that for this application it will not have a noticeable effect.

Note2: S1, 2, 3, and 4 are spst placed there only for the simplicity of the simulation, and they are not considered for the final design.

enter image description here

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  • \$\begingroup\$ Driving of the FETs looks about correct. What I don't understand why there is U4 and U6 in series, and U1 and U3 in series, why can't it simply use U3 and U6 only when U1 and U4 are removed completely? \$\endgroup\$
    – Justme
    Commented Jan 20, 2021 at 9:54
  • \$\begingroup\$ Having only one pair of MOSFETs would produce a shoot-through at some specific point in time when they are changing state. That is why the second pair is included. \$\endgroup\$
    – Smart_Celery
    Commented Jan 20, 2021 at 10:02
  • \$\begingroup\$ And exactly how two pairs prevent that? Wouldn't it be better to turn one FET off first, and after some dead time, turn on the other FET? You would need the dead time to control a pair of FETs in series too, right? \$\endgroup\$
    – Justme
    Commented Jan 20, 2021 at 10:04
  • \$\begingroup\$ you're right. Something missing from the schematic is that I also want to reduce the number of GPIOS. Therefore, GPIO_OE1 and GPIO_OE2 could be connected to the same GPIO, that way the output-enable (or HIGH-Z state) is controlled with a single terminal. I am also considering reducing GPIO1 and GPIO2 to just one terminal by implementing an inverter (not gate), but I have very tight size restrictions. \$\endgroup\$
    – Smart_Celery
    Commented Jan 20, 2021 at 10:08
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    \$\begingroup\$ You need two GPIOs anyway because you have three (or four) states: output high, output low, off. That is exactly same amount of GPIOs to control two fets directly, high FET on/off and low FET on/off. Less space wasted on useless FETs and inverters. \$\endgroup\$
    – Justme
    Commented Jan 20, 2021 at 10:16

1 Answer 1

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Yes, the circuit for driving high side PMOS and low side NMOS FETs looks correct and should work in theory.

Actual performance will vary due to exact part numbers are not known.

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