I am designing a sort of "driver" for a high voltage Charlieplexed LED array, since normal GPIOS can't handle 12V. For that, I need to be able to use tri-state logic, which means LOW, HIGH, and HIGH-Z.
The schematic below shows two arrangements of PMOS and NMOS similar to a push-pull configuration using two of these ICs plus two not yet defined NMOS. The first -U1 and U4- define the behavior that can be represented as push and pull, and the second -U3 and U6- are the output enable. (HIGH means enable and LOW means HIGH-Z)
So far, the simulation is running well, however, In the last question I asked someone made me a heads-up about the ideal behavior of the GPIOs and that I should be careful with the 12V present in the gate of the PMOS. To solve that I included these two NMOS -U5 and U2- keeping the voltage of the GPIOS under safe values.
Is this fix correct? can someone note me if I might be overseeing something, I'm still a noob at this. Also, I'm simulating with NI Multisim 14.2
Note1: I'm aware of the body effect difference that U1 and U4 will have with respect to U3 and U6 since the body/bulk terminal is kept shorted to the source terminal and not Vcc/Vss. However, I think that for this application it will not have a noticeable effect.
Note2: S1, 2, 3, and 4 are spst placed there only for the simplicity of the simulation, and they are not considered for the final design.