VHDL Counter not Working

Question

I have code below for a counter that sets an output bit high or low depending on the count value being compared with a reference value. It is used to generate a PWM signal.

During simulation, the PWM_Output bit is always high as I think the Count_Value signal in never incremented inside the if statement.

Any ideas as to why this PWM_Output bit is not toggling? (Sorry, I am unsure how to get the code in one snippet, maybe someone who knows how will edit the question).

Below is the code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Data_Sizes_Package.all;

entity PWM_Counter_and_Comparator is

    Generic
    (
        Max_Counter_Value : integer := 20
    );

    Port
    (
        PWM_Comparison_Value    : in std_logic_vector(27 downto 0);
        Clock                   : in std_logic;
        Run_Reset               : in std_logic;
        PWM_Output              : out std_logic
    );

end PWM_Counter_and_Comparator;

architecture Behavioral of PWM_Counter_and_Comparator is

    signal PWM_Comparison_Value_int : integer range 0 to Max_Counter_Value;
    signal Count_Value : integer range 0 to Max_Counter_Value;

begin

    PWM_Comparison_Value_int <= conv_integer(unsigned(PWM_Comparison_Value));

    process(Clock, Run_Reset)
    begin

        if Run_Reset = '0' then
            Count_Value <= 0;

            if Count_Value = Max_Counter_Value then
                Count_Value <= 0;

                if (Run_Reset = '1') and (Count_Value < PWM_Comparison_Value_int) then
                    Count_Value <= Count_Value + 1;
                end if;

            end if;

        end if;

    end process;

    process(Clock , Run_Reset)

    begin

        if (Count_Value < PWM_Comparison_Value_int) and (Run_Reset = '1') then
            PWM_Output <= '1';
        else
            PWM_Output <= '0';
        end if;

    end process;

end Behavioral;

Answer 1

Your if statements are nested, so if Run_Reset = '1', the entire process is skipped, and if Run_Reset = '0', the counter is reset and the increment code is skipped. The counter can never take on any other value than zero.

Answer 2

Consider using the standard libraries numeric_std and numeric_std_unsigned instead of std_logic_arith and std_logic_unsigned.

The below example is the standard form for a clocked process with an asynchronous reset for VHDL-2008. I'm not sure what PWM comparator logic you require, so I'll let you decide what to put:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.numeric_std_unsigned.all;  -- Standard library.
--use work.Data_Sizes_Package.all;

entity PWM_Counter_and_Comparator is

    Generic
    (
        Max_Counter_Value : integer := 20
    );

    Port
    (
        PWM_Comparison_Value    : in std_logic_vector(27 downto 0);
        Clock                   : in std_logic;
        Reset                   : in std_logic;
        PWM_Output              : out std_logic
    );

end PWM_Counter_and_Comparator;

architecture Behavioral of PWM_Counter_and_Comparator is

    signal Count_Value : integer range 0 to Max_Counter_Value;

begin

    process(all)  -- For VHDL-2008, use all to replace the sensitivity list.
    begin

        if Reset then  -- Asynchronous reset condition.

            Count_Value <= 0;
            PWM_Output <= '0';

        elsif rising_edge(Clock) then  -- Synchronous logic

            if Count_Value = Max_Counter_Value then
                Count_Value <= 0;
                PWM_Output <= not PWM_Output;  -- Outputs are readable in VHDL-2008.
                                               -- Toggles the output every time Count_Value equals Max_Counter_Value.
                                               -- I'm not sure if this was your intent, so I'll leave it up to you to decide.
            else
                Count_Value <= Count_Value + 1;
            end if;

        end if;

    end process;

end Behavioral;