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I have a four layered PCB with two major high frequency component placed on the top layer. One is JN5169 and other is SE2431l (front end module), both operate in GHz. While evaluating the circuit (with the help of gerber file) I noticed a long trace and I have studied that long traces would add to EMI.

Will it be a good practice if the SE2431l was placed on bottom layer and JN5169 on top and both connected through vias? But I have also read that when dealing with high frequency components vias should be avoided as it would lead to impedance mismatch and hence would lead to EMI.

So my question is what to prefer? My ultimate aim is to reduce the EMI on the board.

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    \$\begingroup\$ In RF design, it is not merely about 1 long trace or some nets with vias.. The high dv/dt and di/dt are not confined to one or two nodes. All the nodes that have fast changes must be properly laid out, especially with respect to return currents and proximity to sensitive nodes. long traces & vias are not so terrible, if return currents are properly laid out. short traces with bad layout are far worse than long traces with proper layout. It is a complicated situation for brief suggestions, but if at all possible it should be based on a layout screenshot and/or schematic \$\endgroup\$
    – tobalt
    May 10 at 11:49
  • \$\begingroup\$ Four layer PCB and GHz sounds tricky. Not impossible, but tricky. \$\endgroup\$
    – winny
    May 10 at 12:08
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Vias, if properly designed, have can have little or no significant impact on RF performance. We build RF modules all the time, using various substrates, stackups, and layer counts, operating at frequencies into the 40 GHz range.

But, every type of via is modeled with a field solver like HFSS or CST Microwave, and the results of that model added to a chain model (like ADS) of the entire RF path to ensure that the entire path meets performance requirements.

Also, there is always a ring of ground vias around the signal via, whose placement and spacing is adjusted to make sure the impedance of the signal via is correct.

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In such a situation you have to weigh the compromises. Ideally you place the components right next to each other. If you can't, you should consider the parasitic inductance of the long trace and compare it to the pi-model corresponding to the via you'd be using. It sounds like you already have a circuit model, so just add the via in. The via if properly implemented has the advantage of not leading to significant EMI but may lead to other issues. I would personally question what prevents you from putting these components in close proximity.

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  • \$\begingroup\$ Thanks for the answer. The components are placed close to each other , i was just asking about the other possibilities and which one would be best one for least emi generation. \$\endgroup\$ May 10 at 11:37

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