How do y1 and y2 take on two different values here? Can someone please explain the order of assignments?

Question

The following code snippet is an example from a SNUG 2000 paper that explains race conditions. The explanation for the race condition is given below, but I do not understand it. How is y1 and y2 = 1 if the first always block executes first? Or 0 if the second block executes first? Can someone please explain the order of execution each statement?

Moreover, when the explanation says "after a reset", does it mean after a reset signal is asserted or de-asserted?

Code:

module fbosc1 (y1, y2, clk, rst);
 output y1, y2;
 input clk, rst;
 reg y1, y2;

 always @(posedge clk or posedge rst)
 if (rst) y1 = 0; // reset
 else y1 = y2;

 always @(posedge clk or posedge rst)
 if (rst) y2 = 1; // preset
 else y2 = y1;
endmodule

Explanation:

According to the IEEE Verilog Standard, the two always blocks can be scheduled in any order. If the first always block executes first after a reset, both y1 and y2 will take on the value of 1. If the second always block executes first after a reset, both y1 and y2 will take on the value 0. This clearly represents a Verilog race condition.

Answer 1

This example is intended to show two registers swapping their values on a clock edge. "After reset" means after reset is de-asserted, but before the next posedge clock edge. In that period of time, y1 is 0 and y2 is 1.

So when the posedge clk, occurs, either the y1 = y2; assignment happens first, or the y2 = y1; happens first. Either way, the "other" value gets lost.

By changing the assignments to NBA <= both assignments use the previous values of y1 and y2, so the order of assignments no longer matters.