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I'm working on a precision DC measurement PCB design based on the capacitance-integration method. The key element integration capacitor is quite precise. However, due to my specific PCB layout design, I found the actual capacitance is a few pF larger than expected.

There're several possible parasitic error sources as I analyzed. The question is how to position the primary source. PowerSI (Cadence Sigrity) is the tool that I tried, but I think it's used to simulate the PDN rather than the impedance between any two terminals.

My question is, which tool is suitable for my parasitic capacitance simulation? Thank you!

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    \$\begingroup\$ Can't you just measure that capacitance? PCBs are cheap, so if you have other things to do while waiting for prototypes, it'll be way cheaper than simulation software. Also, PCB capacitances may well be worse-behaved than good capacitors (e.g. teflon dielectric). In any case, though, the whole idea with integrator-based DC measurements is that the absolute capacitance value should not matter. It varies with temperature, humidity, age, etc. You need to measure it together with each DC measurement. A dual-slope integrator takes care of it. \$\endgroup\$
    – Kuba hasn't forgotten Monica
    Commented Jun 13, 2023 at 1:59
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    \$\begingroup\$ It is extremely hard to beat commercial A/D converters. See e.g. the CERN 8.5-digit open-source voltmeter. I don't know your requirements, but that one uses an off-the-shelf ADC, and very little magic really - mostly off-the-shelf components, but in an excellent system design. Its core is the AD7177-2 32-bit ADC. \$\endgroup\$
    – Kuba hasn't forgotten Monica
    Commented Jun 13, 2023 at 2:03

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