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So let's take a simple cmos circuit like this:
enter image description here

So I get that for DC analysis \$V_G = 12 \frac{R_2}{R_1+R_2} \$ and then \$ V_{GS} \$ makes sense to me...because there is a constant \$ V_G \$ value and there will be a drop....

What doesn't make sense to me is during AC analysis that capacitor becomes a short and \$ V_{in} = v_g \$ and then we have \$ v_{gs} \$, but this value is always changing because \$ V_{in} \$ is a sin wave....so how can we say that \$ v_{gs} \$ is an actual value?

What's more is that \$ v_{GS} = V_{GS} + v_{gs} \$ but again...I'm so lost as to how \$ v_{gs} \$ can be a constant value...any ideas? Thanks

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2 Answers 2

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In order to design the circuit you consider two conditions. The first condition is the DC analysis. This is where you are mainly interested in setting the gate voltage so that the drain voltage is roughly at midpoint on the supply. In your example, midpoint is somewhere close to 6V because you have a 12V supply.

Why is it 6V? When you have 6V DC on the drain, and have AC signals superimposed, those ac signals can rise and fall without needlessly crashing into the 12V region or the 0V region i.e. you have designed the DC conditions that are optimum for your ac signal - Getting the DC conditions right is a bit like making a bed properly - you will have a better night's sleep and not roll to one side and crash into the floor!! (I know it's a bad metaphor)

So, the DC is now right - forget about the DC now and concentrate on what the AC has to face. AC, as a decent approximation sees resistors as resistors BUT capacitors as short-circuits - you wouldn't couple your input to an amp through a capacitor that was too high an impedance - there would be no-point so, caps are regarded as short circuits in AC analysis.

The DC conditions are already defined in the DC analysis but the AC signal will see R1 and R2 as AC loads to ground - the power supply is just DC and it can be regarded as a big capacitor so it is shorted. This now means you can calculate the input impedance of the circuit - it's the parallel combination of R1 and R2.

The gain of the amplifier is also defined by the drain and source resistors, Gm of the JFET and the inherent slope of the drain I/V characteristic. I'm not going to go any further because I hope you might be getting the idea. Feel free to ask questions.

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This is called small signal analysis and is predicated upon an assumption that your small signal doesn't disturb the operating point too much so that the assumptions still hold.

What is key is that that you use the bias points to determine the \$g_m\$ (which will depends upon \$I_{DS}\$ which depends upon \$V_{gs}\$ etc.).

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  • \$\begingroup\$ so are you saying that even though \$ v_{GS} = V_{GS} + v_{gs} \$, really \$ v_{GS} \approx V_{GS} \$ because \$ v_{gs} \$ is so small? Because if so, that would make more sense.... \$\endgroup\$
    – Richard
    Commented Apr 26, 2013 at 5:35
  • \$\begingroup\$ until it gets too big! there are also a whole set of simplifying assumptions that go along with it. This is how SPICE works too. \$\endgroup\$ Commented Apr 26, 2013 at 5:37
  • \$\begingroup\$ but what I don't understand is, let's say \$ R_1 = 50k\Omega \$ and \$ R_2 = 75k\Omega \$. Then \$ V_{G} = V_{GS} = 7.2V \$. Then during AC analysis, if \$ V_{in-peak} = 1V \$, are you saying \$ v_{gs} \$ is still going to be 7.2V? Why would it not be 1V? \$\endgroup\$
    – Richard
    Commented Apr 26, 2013 at 5:45
  • \$\begingroup\$ Once you understand what the operating point is your solve for gains in terms of \$g_m*R\$ for example. You're looking at small perturbations around that point. obviously 1 V is too much. \$\endgroup\$ Commented Apr 26, 2013 at 6:04
  • \$\begingroup\$ ..I'm not sure how that answers my question, sorry, maybe you are answering it and I'm just not understanding....So from my example that I mentioned previous, what would \$ v_{gs} \$ be? \$\endgroup\$
    – Richard
    Commented Apr 26, 2013 at 6:17

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