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Here is what I am wondering. Is the example PCB layout fine for handling bypass capacitors? Or, do I need to run a separate VIA as well? Note that the blue caps are on the backside of the PCB.

Also, I understand that this layout is incomplete, I'm just curious about the shared via. :-)

enter image description here

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  • \$\begingroup\$ Should be listed in the application note. Having one via to two capacitors will have approximately twice the inductance compared to two vias. In general, the BGA pitch will determine the minimum via size and pad-to-via distance needed (and to some extent if you need buried and blind vias), which in the end should allow you to place as many vias as needed, even if that's one per pin. \$\endgroup\$
    – winny
    Commented Aug 15, 2023 at 12:15
  • \$\begingroup\$ Why do you think you need two separate caps on that one Vcc pad? It's not like you're hurting for Vcc (or GND) pads on a big part like that. \$\endgroup\$
    – SteveSh
    Commented Aug 15, 2023 at 12:34
  • \$\begingroup\$ I'm thinking both N8 and N7 need a separate cap \$\endgroup\$
    – Kevin McQuown
    Commented Aug 15, 2023 at 12:38
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    \$\begingroup\$ If you can fit a 2nd via, do it. If not, try to make the via diameter larger. If you can't even do that, then you're stuck with what you've got (assuming you can't pay for via-in-pad). If you don't have any power integrity simulation tool you're stuck just doing the best you can and hoping for success. Whether that's good enough depends how clever you are and how good the chip designers and the app notes from the chip vendor are. \$\endgroup\$
    – The Photon
    Commented Aug 15, 2023 at 15:28
  • \$\begingroup\$ What frequencies is involved, or what power delivery network impedance the BGA device requires? \$\endgroup\$
    – Justme
    Commented Aug 15, 2023 at 15:53

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